Liyang Lai

19 papers A 6C 1Misc 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2025 A conf
An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems.
DATE
Xiaoze Lin, Liyang Lai, Huawei Li, Biwei Xie, Xingquan Li
2024 J jnl
Parallel Static Learning Toward Heterogeneous Computing Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoze Lin, Liyang Lai, Huawei Li
2024 — conf
Sideway Scan, Solving the Achilles' Heel of Scan-based Diagnosis.
ITC-Asia
Liyang Lai, Zefan Lin, Qitao Wang
2023 J jnl
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jingbo Hu, Guohao Dai, Liuzheng Wang, Liyang Lai, Yu Huang, Huazhong Yang, Yu Wang
2023 A conf
GPU-Based Concurrent Static Learning.
ITC
Huaxiao Liang, Xiaoze Lin, Liyang Lai, Naixing Wang, Yu Huang, Fei Yang, Yuxin Yang
2021 — conf
Scalable Parallel Static Learning.
ITC-Asia
Xiaoze Lin, Liyang Lai, Huawei Li
2020 J jnl
GPGPU-Based ATPG System: Myth or Reality?
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liyang Lai, Kun-Han Tsai, Huawei Li
2020 — conf
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns.
ITC-Asia
Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 J jnl
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013 A conf
Diagnosis and Layout Aware (DLA) scan chain stitching.
ITC
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2009 Misc conf
STDF Memory Fail Datalog Standard.
VTS
Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon
2008 A conf
Detection and Diagnosis of Static Scan Cell Internal Defect.
ITC
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
2007 — conf
Programmable Scan-Based Logic Built-In Self Test.
ATS
Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht
2007 J jnl
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Des. Test Comput.
Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006 A conf
Signature Based Diagnosis for Logic BIST.
ITC
Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill
2005 C conf
Hardware Ef.cient LBISTWith Complementary Weights.
ICCD
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2005 — —
New Techniques for Logic Built -in Self -Test
Liyang Lai
2004 Misc conf
Logic BIST Using Constrained Scan Cells.
VTS
Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel
2004 A conf
Logic BIST with Scan Chain Segmentation.
ITC
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng