Liuting Shang

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liuting Shang, Sheng Lu, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 J jnl
A Novel RFET-Based FPGA Architecture Based on Delay-Aware Packing Algorithm.
IEEE Trans. Emerg. Top. Comput.
Sheng Lu, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 — conf
Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node.
ISQED
Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Qilian Liang, Chenyun Pan
2025 J jnl
Technology/System Co-Optimization for FPGA Using Emerging Reconfigurable Logic Device.
ACM J. Emerg. Technol. Comput. Syst.
Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Qilian Liang, Chenyun Pan
2024 — conf
A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET.
MWSCAS
Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Chenyun Pan
2024 — conf
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization.
ISQED
Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan
2023 — conf
A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices.
MWSCAS
Sheng Lu, Zhenlin Pei, Liuting Shang, Sungyong Jung, Chenyun Pan
2023 — conf
Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis.
MWSCAS
Liuting Shang, Sheng Lu, Sungyong Jung, Chenyun Pan
2023 J jnl
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis.
IEEE Open J. Comput. Soc.
Liuting Shang, Azad Naeemi, Chenyun Pan
2020 — conf
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator.
ISVLSI
Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan
2018 J jnl
SRMC: A Multibit Memristor Crossbar for Self-Renewing Image Mask.
IEEE Trans. Very Large Scale Integr. Syst.
Liuting Shang, Shukai Duan, Lidan Wang, Tingwen Huang