Liter Siek - RankMe

89 papers C 20Journal 32Unranked 37

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 310 nA DCM Hysteretic Buck Converter With 95.8% Peak Efficiency and Greater Than 90% Efficiency in 10 μA-100 mA Load Range for Battery Powered IoT Sensors. IEEE Trans. Circuits Syst. I Regul. Pap. Ziming Liu, Wang Ling Goh, Liter Siek, Yuan Gao
2025	—	`conf`	Adaptive Active Balancing in Battery Management Systems with Comprehensive System Modeling. ICEIC Wu Cong Lim, Boon Chiat Terence Teo, Xian Yang Lim, Liter Siek, Eng Leong Tan
2024	—	`conf`	Comparative Analysis of Passive, Active, and Hybrid Cell Balancing for Optimal Battery Performance. ICEIC Wu Cong Lim, Boon Chiat Terence Teo, Xian Yang Lim, Liter Siek, Eng Leong Tan
2024	J	`jnl`	Recent Development of High-PCE CMOS RF-DC Rectifier With Wide P IEEE Access Boon Chiat Terence Teo, Wu Cong Lim, Xian Yang Lim, Venkadasamy Navaneethan, Liter Siek
2023	—	`conf`	A Battery-input Hysteretic Buck Converter with 430nA Quiescent Current and 5×10 BioCAS Ziming Liu, Wang Ling Goh, Liter Siek, Yuan Gao
2023	—	`conf`	A Review on Current-Steering DAC Design. ICEIC Xian Yang Lim, Wu Cong Lim, Boon Chiat Terence Teo, Venkadasamy Navaneethan, Chong Boon Tan, Nardi Utomo, Liter Siek, Atila Alvandpour
2023	J	`jnl`	An 85.1% Peak Efficiency, Low Power Class H Audio Amplifier With Full Class H Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Liter Siek
2023	—	`conf`	Performance Analysis of Self-biasing Technique for Differential RF-DC Rectifier in IoT Application. ICEIC Boon Chiat Terence Teo, Wu Cong Lim, Xian Yang Lim, Venkadasamy Navaneethan, Chong Boon Tan, Nardi Utomo, Liter Siek
2022	J	`jnl`	An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Gibran Limi Jaya, Chirn Chye Boon, Shoushun Chen, Liter Siek
2022	—	`conf`	Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. MIXDES Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek
2021	J	`jnl`	A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique. IEEE Access Ao Zhou, Xin Ding, Chirn Chye Boon, Liter Siek, Yuan Liang, Yangtao Dong
2021	C	`conf`	A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application. ISCAS Teo Boon Chiat Terence, Venkadasamy Navaneethan, Lim Xian Yang, Nardi Utomo, Ziming Liu, Tan Chong Boon, Seah Yun Da Bryan, Ji-Jon Sit, Liter Siek
2021	—	`conf`	A digital switching scheme to reduce DAC glitches using code-dependent randomization. NorCAS Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek
2021	C	`conf`	Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference. ISCAS Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Yun Da Bryan Seah, Ying Hung Yvonne Lam, Liter Siek
2020	—	`conf`	A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. NorCAS Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek
2020	J	`jnl`	Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting. IEEE Trans. Circuits Syst. Wendy Wee Yee Lau, Heng Wah Ho, Liter Siek
2019	C	`conf`	A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. ISCAS Arjun Ramaswami Palaniappan, Liter Siek
2019	J	`jnl`	A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Devrishi Khanna, Chirn Chye Boon, Pilsoon Choi, Liter Siek, Bei Liu, Chenyang Li
2019	J	`jnl`	A Single-Stage Dual-Output Tri-Mode AC-DC Regulator for Inductively Powered Application. IEEE Trans. Circuits Syst. I Regul. Pap. Qiong Wei Low, Liter Siek
2019	J	`jnl`	A TDC-less all-digital phase locked loop for medical implant applications. Microprocess. Microsystems Arjun Ramaswami Palaniappan, Liter Siek
2019	J	`jnl`	Multiloop Control for Fast Transient DC-DC Converter. IEEE Trans. Very Large Scale Integr. Syst. Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek
2018	—	`conf`	A 0.0186 mm NORCAS Arjun Ramaswami Palaniappan, Liter Siek
2018	J	`jnl`	A 0.058 mm Circuits Syst. Signal Process. Di Zhu, Liter Siek
2018	C	`conf`	A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. ISCAS Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa
2018	J	`jnl`	A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U
2018	C	`conf`	A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module. ISCAS Mi Zhou, Zhuochao Sun, Zhekai Xiao, Qiong Wei Low, Liter Siek
2018	J	`jnl`	A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application. IEEE Trans. Very Large Scale Integr. Syst. Qiong Wei Low, Mi Zhou, Liter Siek
2018	—	`conf`	An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage. NORCAS Nardi Utomo, Liter Siek, Heng Goh Yap, Don Disney, Lawrence Selvaraj, Lulu Peng
2018	C	`conf`	Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration. ISCAS Jian Sen Teh, Liter Siek
2017	C	`conf`	A 0.9-V input PWM DCM boost converter with low output ripples and fast load transient response based on a novel square-root voltage mode (SRVM) control approach. ISCAS Hao Luo, Liter Siek
2017	J	`jnl`	A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission. IEEE Trans. Very Large Scale Integr. Syst. Xiaoyin Bai, Zhi-Hui Kong, Liter Siek
2017	J	`jnl`	A Hysteretic Switched-Capacitor DC-DC Converter With Optimal Output Ripple and Fast Transient Response. IEEE Trans. Very Large Scale Integr. Syst. Zhekai Xiao, Anh Khoa Bui, Liter Siek
2017	J	`jnl`	A transient-enhanced low dropout regulator with rail to rail dynamic impedance attenuation buffer suitable for commercial design. Microelectron. J. Kan Li, Yuanjin Zheng, Liter Siek
2017	J	`jnl`	An 80.4% Peak Power Efficiency Adaptive Supply Class H Power Amplifier for Audio Applications. IEEE Trans. Very Large Scale Integr. Syst. Xiang Zhang, Liter Siek
2016	J	`jnl`	A 1 V 103 dB 3rd-Order Audio Continuous-Time ΔΣ ADC With Enhanced Noise Shaping in 65 nm CMOS. IEEE J. Solid State Circuits Yoon Hwee Leow, Howard Tang, Zhuochao Sun, Liter Siek
2016	—	`conf`	A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. A-SSCC Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U
2016	—	`conf`	A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. APCCAS Junjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek
2016	J	`jnl`	A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs. Circuits Syst. Signal Process. Lei Qiu, Yuanjin Zheng, Liter Siek
2016	J	`jnl`	A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs. IEEE Trans. Very Large Scale Integr. Syst. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek
2016	C	`conf`	A close-loop time-mode temperature sensor with inaccuracy of -0.6°C/0.5°C from -40°C to 120°C. ISCAS Di Zhu, Jiacheng Wang, Liter Siek
2016	—	`conf`	A continuous switching mode step-down switched-capacitor regulator with inrush current control scheme. ISIC Chengyue Yu, Xiang Zhang, Liter Siek
2016	—	`conf`	A dual redundancy radiation-hardened Flip-Flop based on C-element in 65nm process. ISIC Gibran Limi Jaya, Shoushun Chen, Liter Siek
2016	—	`conf`	A high efficiency synchronous buck converter with adaptive dead-time control. ISIC Mi Zhou, Qiong Wei Low, Liter Siek
2016	—	`conf`	A switched-capacitor DC-DC converter with embedded fast NMOS-LDOs achieving low noise, low output voltage ripple and fast response. ISIC Zhekai Xiao, Anh Khoa Bui, Liter Siek
2016	J	`jnl`	Asymmetrical Dead-Time Control Driver for Buck Regulator. IEEE Trans. Very Large Scale Integr. Syst. Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Liter Siek, Yat-Hei Lam, Xi Zhu, Ravinder Pal Singh
2016	—	`conf`	Digitally-controlled H-bridge DC-DC converter for micropower PV energy harvesting system. ISIC Anh Khoa Bui, Zhekai Xiao, Liter Siek
2016	—	`conf`	Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter. ISIC W. L. Tan, C. H. Chang, Liter Siek
2016	J	`jnl`	High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications. Circuits Syst. Signal Process. Di Zhu, Liter Siek, Yuanjin Zheng
2016	J	`jnl`	Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal. Circuits Syst. Signal Process. Lei Qiu, Yuanjin Zheng, Liter Siek
2016	—	`conf`	Performance analysis on active rectifier structures for inductively powered application. ISIC Qiong Wei Low, Mi Zhou, Liter Siek
2016	—	`conf`	Review of pulse generators for gated ring oscillator based Time-to-Digital converters. ISIC Jian Sen Teh, Arjun Ramaswami Palaniappan, Liter Siek, Yuanjin Zheng
2015	J	`jnl`	A 400 nW Single-Inductor Dual-Input-Tri-Output DC-DC Buck-Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting. IEEE J. Solid State Circuits Guolei Yu, Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek
2015	C	`conf`	A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology. ISCAS Junjie Kong, Liter Siek, Chiang Liang Kok
2015	J	`jnl`	A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor. J. Circuits Syst. Comput. Di Zhu, Liter Siek
2015	C	`conf`	A digital time skew calibration technique for time-interleaved ADCs. ISCAS Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek
2015	C	`conf`	A high efficiency rectifier for inductively power transfer application. VLSI-SoC Qiong Wei Low, Liter Siek, Mi Zhou
2015	C	`conf`	A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. ISCAS Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek
2015	—	`conf`	A low TC, supply independent and process compensated current reference. CICC Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Wanlan Yang, Liter Siek
2015	C	`conf`	A switched capacitor deadtime controller for DC-DC buck converter. ISCAS Chiang Liang Kok, Xin Li, Liter Siek, Di Zhu, Junjie Kong
2015	J	`jnl`	An Area-Efficient Current-Mode Bandgap Reference With Intrinsic Robust Start-Up Behavior. IEEE Trans. Circuits Syst. II Express Briefs Chengyue Yu, Liter Siek
2015	C	`conf`	Design of WPT coils to minimize AC resistance and capacitor stress applied to SS-topology. IECON Robin Tanzania, Fook Hoong Choo, Liter Siek
2014	J	`jnl`	A 0.42-V Input Boost dc-dc Converter With Pseudo-Digital Pulsewidth Modulation. IEEE Trans. Circuits Syst. II Express Briefs Zhuochao Sun, Kin Wai Roy Chew, Howard Tang, Guolei Yu, Liter Siek
2014	J	`jnl`	A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory. Neurocomputing Fei Li, Chip-Hong Chang, Arindam Basu, Liter Siek
2014	J	`jnl`	A 1.33 µW 8.02-ENOB 100 kS/s Successive Approximation ADC With Supply Reduction Technique for Implantable Retinal Prosthesis. IEEE Trans. Biomed. Circuits Syst. Howard Tang, Zhuochao Sun, Kin Wai Roy Chew, Liter Siek
2014	J	`jnl`	A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device. IEEE Trans. Very Large Scale Integr. Syst. Howard Tang, Zhuochao Sun, Kin Wai Roy Chew, Liter Siek
2014	C	`conf`	A Fixed-frequency hysteretic controlled buck DC-DC converter with improved load regulation. ISCAS Zhuochao Sun, Liter Siek, Ravinder Pal Singh, Minkyu Je
2014	C	`conf`	A statistic based time skew calibration method for time-interleaved ADCs. ISCAS Lei Qiu, Yuanjin Zheng, Di Zhu, Liter Siek
2014	—	`conf`	High accuracy time-mode duty-cycle-modulation-based temperature sensor for energy efficient system applications. ISIC Di Zhu, Jiacheng Wang, Liter Siek, Chiang Liang Kok, Lei Qiu, Yuanjin Zheng
2014	—	`conf`	Triple boundary multiphase with predictive interleaving technique for switched capacitor DC-DC converter regulation. ISIC Zhekai Xiao, Chiang Liang Kok, Liter Siek
2013	—	`conf`	A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting. ISSCC Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek
2013	C	`conf`	Analysis and design of high performance frequency-interleaved ADC. ISCAS Lei Qiu, Yuanjin Zheng, Liter Siek
2012	J	`jnl`	A Novel Ultra-Low Power Two-Terminal Zener voltage Reference. J. Circuits Syst. Comput. Chiang Liang Kok, Liter Siek, Wei Meng Lim
2012	—	`conf`	A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
2012	—	`conf`	A fully digital green LDO regulator dedicated for biomedical implant using a power-aware binary switching technique. APCCAS Chiang Liang Kok, Qi Huang, Di Zhu, Liter Siek, Wei Meng Lim
2012	C	`conf`	A novel analog-to-residue conversion scheme based on clock overlapping technique. ISCAS Qi Huang, Di Zhu, Liter Siek
2012	—	`conf`	A novel analog-to-residue converter for biomedical DSP application. ISOCC Di Zhu, Qi Huang, Zhao Chuan Lee, Yuanjin Zheng, Liter Siek
2012	—	`conf`	An ultra-compact green bio-regulator dedicated for brain cortical implant using a dynamic PSR enhancement technique. EMBC Chiang Liang Kok, Liter Siek, Fei Gao, Yuanjin Zheng, Wei Meng Lim
2010	—	`conf`	A high speed tracking quantizer for Continuous-Time multi-bit sigma delta modulators. APCCAS Yoon Hwee Leow, Liter Siek
2010	—	`conf`	A simplified approach for baseband recovery in SDR architectures. APCCAS Richard Wee Tar Ng, Liter Siek
2010	—	`conf`	Analog-to-Digital Converter with energy recovery capability using adiabatic technique. APCCAS Howard Tang, Liter Siek
2009	C	`conf`	A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. ISCAS Fei Li, Chip-Hong Chang, Liter Siek
2009	J	`jnl`	A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning. IEEE Trans. Very Large Scale Integr. Syst. Hai Qi Liu, Wang Ling Goh, Liter Siek, Wei Meng Lim, Yue Ping Zhang
2007	—	`conf`	A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC. SoCC Yuan Sun, Liter Siek
2007	—	`conf`	A two-step dynamic reference A/D converter. ECCTD Danping Li, Liter Siek
2005	—	`conf`	1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology. SoCC Hai Qi Liu, Wang Ling Goh, Liter Siek
2005	—	`conf`	A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers. ISCAS (2) Hai Qi Liu, Wang Ling Goh, Liter Siek
2005	—	`conf`	A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage. ISCAS (5) Q. X. Zhang, Liter Siek
2000	C	`conf`	A low-offset class-AB CMOS operational amplifier. ISCAS Pak K. Chan, Liter Siek, Hwee C. Tay, Jing H. Su
1999	—	`conf`	Bulk compensated CMOS squaring circuits. ISCAS (2) Pak Kwong Chan, L. S. Ng, Liter Siek, M. S. Tse, J. Y. Ong, K. S. Lok