Lirida Alves de Barros Naviner

29 papers A 1B 1C 1Journal 9Unranked 17
YearRankTypeTitle / Venue / Authors
2024 — conf
nMatrix: A New Decoding Algorithm for the Matrix ECC.
LADC
David C. C. Freitas, Lirida Alves de Barros Naviner, João Cesar Moura Mota, Jarbas Silveira, César A. M. Marcon, David Freitas Moura Mota, Alexandre A. P. Coelho
2023 J jnl
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.
IEEE Des. Test
Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner
2022 J jnl
Writing-only in-MRAM computing paradigm for ultra-low power applications.
Microprocess. Microsystems
Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner
2019 J jnl
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao
2017 J jnl
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Weisheng Zhao
2017 — conf
Sparsity analysis using a mixed approach with greedy and LS algorithms on channel estimation.
ICFSP
Nilson Maciel de Paiva, Elaine Crespo Marques, Lirida Alves de Barros Naviner
2016 J jnl
Efficient reliability evaluation methodologies for combinational circuits.
Microelectron. Reliab.
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner
2015 J jnl
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.
Microelectron. Reliab.
Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, Jean-François Naviner
2015 — conf
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.
NEWCAS
Lirida Alves de Barros Naviner, Hao Cai, You Wang, Weisheng Zhao, Arwa Ben Dhia
2014 — conf
Analytical method for reliability assessment of concurrent checking circuits under multiple faults.
MIPRO
Ting An, Kaikai Liu, Lirida Alves de Barros Naviner
2014 — conf
Analytical methods to assess transient faults effects in logic circuits.
MWSCAS
Lirida Alves de Barros Naviner
2014 — conf
Efficient implementation for accurate analysis of CED circuits against multiple faults.
MIXDES
Ting An, Kaikai Liu, Hao Cai, Lirida Alves de Barros Naviner
2014 C conf
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.
IOLTS
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman
2014 — conf
Reliability-aware delay faults evaluation of CMOS flip-flops.
MIXDES
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner
2014 B conf
Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
ETS
Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman
2014 — conf
Simulation study of aging in CMOS binary adders.
MIPRO
Ting An, Hao Cai, Lirida Alves de Barros Naviner
2013 J jnl
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs.
Microelectron. Reliab.
Arwa Ben Dhia, Samuel N. Pagliarini, Lirida Alves de Barros Naviner, Habib Mehrez, Philippe Matherat
2013 — conf
A low cost reliable architecture for S-Boxes in AES processors.
DFTS
Ting An, Lirida Alves de Barros Naviner, Philippe Matherat
2013 — conf
Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults.
NEWCAS
Ting An, Lirida Alves de Barros Naviner, Philippe Matherat
2013 J jnl
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults.
Microelectron. Reliab.
Samuel N. Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, Jean-François Naviner
2013 A conf
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.
DATE
Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman
2012 — conf
A new fault-tolerant architecture for CLBs in SRAM-based FPGAs.
ICECS
Arwa Ben Dhia, Lirida Alves de Barros Naviner, Philippe Matherat
2012 — conf
Automatic selective hardening against soft errors: A cost-based and regularity-aware approach.
ICECS
Samuel N. Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, Jean-François Naviner
2012 J jnl
Exploring the feasibility of selective hardening for combinational logic.
Microelectron. Reliab.
Samuel N. Pagliarini, G. G. dos Santos, Lirida Alves de Barros Naviner, Jean-François Naviner
2012 — conf
Majority voter: Signal probability, reliability and error bound characteristics.
MWSCAS
Tian Ban, Lirida Alves de Barros Naviner
2012 — conf
Parallel scaling-free and area-time efficient CORDIC algorithm.
ICECS
Matteo Causo, Ting An, Lirida Alves de Barros Naviner
2012 — conf
Transient fault analysis of CORDIC processor.
ICECS
Ting An, Matteo Causo, Lirida Alves de Barros Naviner, Philippe Matherat
2008 — conf
Methods and Metrics for Reliability Assessment.
Fault-Tolerant Distributed Algorithms on VLSI Chips
Lirida Alves de Barros Naviner, Jean-François Naviner, Denis Teixeira Franco, Maí Correia R. de Vasconcelos
2003 — conf
On baseband considerations for multistandard RF receivers.
ICECS
Elizabeth Colin, Lirida Alves de Barros Naviner