Linyan Mei - RankMe

24 papers A* 1A 2B 1C 2Journal 13Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators. IEEE Trans. Computers Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2023	C	`conf`	ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators. ICCD Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst
2023	A*	`conf`	DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. HPCA Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst
2023	A	`conf`	PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2023	—	`conf`	SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. AICAS Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini
2023	J	`jnl`	SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. CoRR Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini
2023	B	`conf`	Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators. ISPASS Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2023	J	`jnl`	TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE J. Solid State Circuits Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst
2023	J	`jnl`	TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. CoRR Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst
2022	A	`conf`	A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné
2022	J	`jnl`	CONVOLVE: Smart and seamless design of smart edge processors. CoRR Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2022	J	`jnl`	DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. CoRR Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst
2022	J	`jnl`	Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation. IEEE Trans. Circuits Syst. I Regul. Pap. Ehab M. Ibrahim, Linyan Mei, Marian Verhelst
2022	—	`conf`	TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. VLSI Technology and Circuits Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst
2022	J	`jnl`	Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks. CoRR Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
2021	—	`conf`	Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks. AICAS Vikram Jain, Linyan Mei, Marian Verhelst
2021	J	`jnl`	Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. Man Shi, Pouya Houshmand, Linyan Mei, Marian Verhelst
2021	—	`conf`	LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation. AICAS Arne Symons, Linyan Mei, Marian Verhelst
2021	C	`conf`	Processor Architecture Optimization for Spatially Dynamic Neural Networks. VLSI-SoC Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst
2021	J	`jnl`	Survey and Benchmarking of Precision-Scalable MAC Arrays for Embedded DNN Processing. CoRR Ehab M. Ibrahim, Linyan Mei, Marian Verhelst
2021	J	`jnl`	ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst
2020	J	`jnl`	ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst
2019	J	`jnl`	Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. Vincent Camus, Linyan Mei, Christian C. Enz, Marian Verhelst
2019	—	`conf`	Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. AICAS Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst