Linxiao Shen - RankMe

73 papers A* 2A 1C 3Journal 33Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Highly Power-Efficient Input-Boosted First Stage for Capacitively Coupled Chopper Instrumentation Amplifiers. IEEE J. Solid State Circuits Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Linxiao Shen
2026	J	`jnl`	An 8b 1-GS/s SAR ADC With Comparison Time Quantizer, Metastability Reduction, and On-Chip Self-Tuning Delay Achieving 47.2-dB SNDR at Nyquist Input. IEEE J. Solid State Circuits Jie Li, Siyuan Ye, Zhuoyi Chen, Jihang Gao, Xinhang Xu, Linxiao Shen
2026	J	`jnl`	An Area-Efficient Noise-Shaping SAR ADC Utilizing Dynamic Common-Gate Amplifier With Charge-Boosted Amplification and Dynamic-Bulk-Switching. IEEE Trans. Circuits Syst. I Regul. Pap. Jiajia Cui, Jihang Gao, Xinhang Xu, Yandong He, Linxiao Shen
2025	—	`conf`	13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction. ISSCC Ying Liu, Jie Li, Qining Zhang, Tianhao Zhao, Chenhao Shi, Ninghui Shang, Peiyu Chen, Xiaohuan Ge, Yufei Ma, Linxiao Shen, Zhixuan Wang, Ru Huang, Le Ye
2025	—	`conf`	18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler. ISSCC Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye, Ru Huang, Linxiao Shen
2025	—	`conf`	18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator. ISSCC Jihang Gao, Yaohui Luan, Siyuan Ye, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Ru Huang, Linxiao Shen
2025	—	`conf`	18.5 A Rail-to-Rail 3 ISSCC Siyuan Ye, Jiajia Cui, Jihang Gao, Jie Li, Xing Zhang, Ru Huang, Linxiao Shen
2025	—	`conf`	6.6 A 320×256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-Paralleled Light-Driven 20b Current-to-Phase ADC. ISSCC Yi Zhuo, Hangyu Lu, Ding Ma, Zheng Zhou, Linxiao Shen, Yacong Zhang, Zhongjian Chen, Xixin Cao, Yimao Cai, Ning Li, Wengao Lu
2025	—	`conf`	A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs. CICC Xinhang Xu, Yaohui Luan, Jie Li, Jihang Gao, Kwok Cheong Li, Jiajia Cui, Ru Huang, Linxiao Shen
2025	J	`jnl`	A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting. IEEE J. Solid State Circuits Siyuan Ye, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Yaohui Luan, Le Ye, Xing Zhang, Ru Huang, Linxiao Shen
2025	J	`jnl`	A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. IEEE J. Solid State Circuits Peiyu Chen, Wentao Zhao, Meng Wu, Linxiao Shen, Tianyu Jia, Ru Huang, Le Ye, Yufei Ma
2025	J	`jnl`	A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping. IEEE J. Solid State Circuits Jihang Gao, Yaohui Luan, Siyuan Ye, Jiajia Cui, Xinhang Xu, Linxiao Shen
2025	J	`jnl`	A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator. IEEE Trans. Circuits Syst. II Express Briefs Kwok Cheong Li, Xinhang Xu, Jihang Gao, Siyuan Ye, Jiajia Cui, Yacong Zhang, Ru Huang, Linxiao Shen
2025	—	`conf`	An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration. ISSCC Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Ru Huang, Linxiao Shen
2025	J	`jnl`	An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. IEEE J. Solid State Circuits Jihang Gao, Siyuan Ye, Jie Li, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Yaohui Luan, Ru Huang, Le Ye, Linxiao Shen
2024	—	`conf`	3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. ISSCC Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye
2024	—	`conf`	9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. ISSCC Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang
2024	—	`conf`	9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. ISSCC Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang
2024	J	`jnl`	A 0.39-mm IEEE J. Solid State Circuits Heyi Li, Kaixuan Du, Yuanxin Bao, Yanchi Dong, Jiayoon Ru, Han Xiao, Hao Zhang, Zhixuan Wang, Yi Zhong, Linxiao Shen, Le Ye, Ru Huang
2024	J	`jnl`	A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs Kaixuan Du, Maoqiang Liu, Zhixuan Wang, Heyi Li, Yuanxin Bao, Linxiao Shen, Le Ye
2024	—	`conf`	An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. CICC Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye
2024	C	`conf`	Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network. ISCAS Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Lifeng Liu, Linxiao Shen, Peng Huang, Xiaoyan Liu, Jinfeng Kang
2024	J	`jnl`	Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2024	J	`jnl`	Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Haozhang Yang, Lifeng Liu, Linxiao Shen, Xiaoyan Liu, Jinfeng Kang, Peng Huang
2023	—	`conf`	A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. ISSCC Yihan Zhang, You You, Wenjie Ren, Xinhang Xu, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye
2023	—	`conf`	A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. ESSCIRC Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye
2023	—	`conf`	A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. ISSCC Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang
2023	—	`conf`	A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. ISSCC Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye
2023	J	`jnl`	A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun
2023	J	`jnl`	An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Ying Liu, Yufei Ma, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye
2023	C	`conf`	An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. ISCAS Yiqi Jing, Zhixuan Wang, Linxiao Shen, Yihan Zhang, Peiyu Chen, Jiayoon Ru, Le Ye
2023	J	`jnl`	Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang
2023	J	`jnl`	Post-Layout Simulation Driven Analog Circuit Sizing. CoRR Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2023	J	`jnl`	Research progress on low-power artificial intelligence of things (AIoT) chip design. Sci. China Inf. Sci. Le Ye, Zhixuan Wang, Tianyu Jia, Yufei Ma, Linxiao Shen, Yihan Zhang, Heyi Li, Peiyu Chen, Meng Wu, Ying Liu, Yiqi Jing, Hao Zhang, Ru Huang
2022	C	`conf`	A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. ISCAS Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye
2022	—	`conf`	A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. CICC Hao Zhang, Linxiao Shen, Shichuang Zhang, Heyi Li, Yihan Zhang, Zhichao Tan, Ru Huang, Le Ye
2022	—	`conf`	An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. ISSCC Ying Liu, Zhixuan Wang, Wei He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang
2022	J	`jnl`	Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
2022	—	`conf`	Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. ISSCC Yihan Zhang, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang
2021	—	`conf`	10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
2021	J	`jnl`	A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. IEEE J. Solid State Circuits Zhixuan Wang, Ying Liu, Peng Zhou, Zhichao Tan, Haitao Fan, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Yangyuan Wang, Le Ye, Ru Huang
2021	J	`jnl`	A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun
2021	—	`conf`	A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun
2021	J	`jnl`	A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. IEEE J. Solid State Circuits Zhixuan Wang, Hao Zhang, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Haitao Fan, Zhichao Tan, Yangyuan Wang, Le Ye, Ru Huang
2021	J	`jnl`	Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. IEEE J. Solid State Circuits Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Linxiao Shen, Jiayoon Ru, Yihan Zhang, Le Ye, Ru Huang
2021	J	`jnl`	The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Le Ye, Zhixuan Wang, Ying Liu, Peiyu Chen, Heyi Li, Hao Zhang, Meng Wu, Wei He, Linxiao Shen, Yihan Zhang, Zhichao Tan, Yangyuan Wang, Ru Huang
2020	—	`conf`	16.5 A 13b 0.005mm ISSCC Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	—	`conf`	9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun
2020	J	`jnl`	A 0.025-mm IEEE J. Solid State Circuits Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2020	J	`jnl`	A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
2020	J	`jnl`	A 13-bit 0.005-mm IEEE J. Solid State Circuits Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	—	`conf`	A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun
2020	—	`conf`	A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun
2020	J	`jnl`	A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun
2020	J	`jnl`	An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun
2020	J	`jnl`	An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
2020	A*	`conf`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	J	`jnl`	GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han
2020	—	`conf`	S ASP-DAC Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2019	—	`conf`	A 0.01mm ISSCC Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019	—	`conf`	A 0.025-mm CICC Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2019	—	`conf`	A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun
2019	—	`conf`	A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
2019	—	`conf`	A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun
2019	J	`jnl`	A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2019	—	`conf`	An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun
2019	—	`conf`	Device Layer-Aware Analytical Placement for Analog Circuits. ISPD Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019	A*	`conf`	WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2018	J	`jnl`	A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. IEEE J. Solid State Circuits Linxiao Shen, Nanshu Lu, Nan Sun
2018	—	`conf`	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun
2017	—	`conf`	NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method. EMBC Hyoyoung Jeong, Taewoo Ha, Irene Kuang, Linxiao Shen, Zhaohe Dai, Nan Sun, Nanshu Lu