Linda S. Milor

30 papers A* 1A 2C 2Misc 3Journal 17Unranked 5
YearRankTypeTitle / Venue / Authors
2016 Misc conf
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs.
VTS
Dae Hyun Kim, Linda S. Milor
2016 J jnl
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Fahad Ahmed, Linda S. Milor
2016 C conf
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection.
ICCD
Taizhi Liu, Chang-Chih Chen, Jiadong Wu, Linda S. Milor
2015 J jnl
AVERT: An elaborate model for simulating variable retention time in DRAMs.
Microelectron. Reliab.
Dae Hyun Kim, Soonyoung Cha, Linda S. Milor
2015 — conf
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines.
ISQED
Taizhi Liu, Chang-Chih Chen, Linda S. Milor
2015 J jnl
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectron. Reliab.
Dae Hyun Kim, Soonyoung Cha, Linda S. Milor
2015 J jnl
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms.
IEEE Trans. Very Large Scale Integr. Syst.
Chang-Chih Chen, Linda S. Milor
2015 J jnl
Processor-level reliability simulator for time-dependent gate dielectric breakdown.
Microprocess. Microsystems
Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor
2015 J jnl
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab.
Soonyoung Cha, Dae Hyun Kim, Taizhi Liu, Linda S. Milor
2014 Misc conf
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
VTS
Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor
2014 J jnl
Simulation of system backend dielectric reliability.
Microelectron. J.
Chang-Chih Chen, Muhammad Bashir, Linda S. Milor, Daehyun Kim, Sung Kyu Lim
2012 J jnl
Statistical model of NBTI and reliability simulation for analogue circuits.
Microelectron. Reliab.
Zhengliang Lv, Linda S. Milor, Shiyuan Yang
2010 J jnl
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.
Microelectron. Reliab.
Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim
2010 A conf
Towards a chip level reliability simulator for copper/low-k backend processes.
DATE
Muhammad Bashir, Linda S. Milor
2009 J jnl
A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation.
Microelectron. Reliab.
Muhammad Bashir, Linda S. Milor
2009 — conf
Fast Variation-Aware Statistical Dynamic Timing Analysis.
CSIE (3)
Seyed-Abdollah Aftabjahani, Linda S. Milor
2009 C conf
Reliable cache design with detection of gate oxide breakdown using BIST.
ICCD
Fahad Ahmed, Linda S. Milor
2009 — conf
Timing Analysis with Compact Variation-Aware Standard Cell Models.
CSIE (3)
Seyed-Abdollah Aftabjahani, Linda S. Milor
2009 J jnl
Timing analysis with compact variation-aware standard cell models.
Integr.
Seyed-Abdollah Aftabjahani, Linda S. Milor
2008 J jnl
A BIST Circuit for DLL Fault Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng Jia, Linda S. Milor
2008 — conf
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.
ISQED
Seyed-Abdollah Aftabjahani, Linda S. Milor
2008 J jnl
Diagnosis of Optical Lithography Faults With Product Test Sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Munkang Choi, Linda S. Milor
2006 J jnl
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Munkang Choi, Linda S. Milor
2005 J jnl
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models.
Microelectron. Reliab.
Changsoo Hong, Linda S. Milor, Munkang Choi, Tom Lin
2003 A conf
A BIST Solution for The Test of I/O Speed.
ITC
Cheng Jia, Linda S. Milor
1996 A* conf
Computing Parametric Yield Adaptively Using Local Linear Models.
DAC
Mien Li, Linda S. Milor
1996 Misc conf
Is High Frequency Analog DFT Possible?
VTS
Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik
1994 J jnl
Minimizing production test time to detect faults in analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Linda S. Milor, Alberto L. Sangiovanni-Vincentelli
1989 J jnl
Detection of catastrophic faults in analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Linda S. Milor, V. Visvanathan
1986 — conf
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
SCG
V. Visvanathan, Linda S. Milor