Linda Milor

53 papers A 4B 1C 3Misc 6Journal 29Unranked 10
YearRankTypeTitle / Venue / Authors
2022 J jnl
CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Zhang, Taizhi Liu, Kexin Yang, Linda Milor
2021 J jnl
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Rui Zhang, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor
2020 — conf
Inverse Design of FinFET SRAM Cells.
IRPS
Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, Wenshan Cai, Linda Milor
2020 J jnl
Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Da Wu, Kexin Yang, Shu-Han Hsu, Linda Milor
2020 J jnl
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations.
IEEE Trans. Very Large Scale Integr. Syst.
Rui Zhang, Taizhi Liu, Kexin Yang, Chang-Chih Chen, Linda Milor
2019 C conf
Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure.
IOLTS
Shu-Han Hsu, Ying-Yuan Huang, Kexin Yang, Linda Milor
2019 — conf
Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor.
IWASI
Rui Zhang, Kexin Yang, Taizhi Liu, Linda Milor
2019 — conf
Machine Learning for Detection of Competing Wearout Mechanisms.
IRPS
Shu-Han Hsu, Kexin Yang, Linda Milor
2019 J jnl
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown.
IEEE Trans. Very Large Scale Integr. Syst.
Dae-Hyun Kim, Shu-Han Hsu, Linda Milor
2019 — conf
Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators.
DCIS
Shu-Han Hsu, Kexin Yang, Linda Milor
2018 J jnl
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor
2018 Misc conf
Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.
VTS
Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor
2018 J jnl
Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors.
IEEE Trans. Emerg. Top. Comput.
Taizhi Liu, Chang-Chih Chen, Linda Milor
2018 — conf
Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.
DCIS
Rui Zhang, Kexin Yang, Taizhi Liu, Linda Milor
2018 — conf
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
DCIS
Kexin Yang, Rui Zhang, Taizhi Liu, Dae Hyun Kim, Linda Milor
2017 Misc conf
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes.
VTS
Dae-Hyun Kim, Linda Milor
2017 — conf
Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs.
IWASI
Soonyoung Cha, Linda Milor
2017 J jnl
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Dae-Hyun Kim, Linda Milor
2017 J jnl
Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test.
Microelectron. Reliab.
Dae-Hyun Kim, Linda Milor
2017 J jnl
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations.
Microelectron. Reliab.
Rui Zhang, Taizhi Liu, Kexin Yang, Linda Milor
2017 J jnl
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectron. Reliab.
Kexin Yang, Taizhi Liu, Rui Zhang, Dae Hyun Kim, Linda Milor
2017 J jnl
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. Very Large Scale Integr. Syst.
Soonyoung Cha, Taizhi Liu, Linda Milor
2017 C conf
On-line monitoring of system health using on-chip SRAMs as a wearout sensor.
IOLTS
Woongrae Kim, Taizhi Liu, Linda Milor
2016 J jnl
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array.
IEEE Trans. Very Large Scale Integr. Syst.
Woongrae Kim, Chang-Chih Chen, Dae Hyun Kim, Linda Milor
2016 J jnl
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.
IEEE Trans. Very Large Scale Integr. Syst.
Chang-Chih Chen, Taizhi Liu, Linda Milor
2015 J jnl
Comprehensive reliability and aging analysis on SRAMs within microprocessor systems.
Microelectron. Reliab.
Taizhi Liu, Chang-Chih Chen, Woongrae Kim, Linda Milor
2015 — conf
Estimation of remaining life using embedded SRAM for wearout parameter extraction.
IWASI
Woongrae Kim, Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda Milor
2015 Misc conf
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array.
VTS
Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor
2015 Misc conf
Panel: Analog/RF BIST: Are we there yet?
VTS
Sule Ozev, Linda Milor
2015 J jnl
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectron. Reliab.
Taizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor
2014 J jnl
Backend Dielectric Reliability Full Chip Simulator.
IEEE Trans. Very Large Scale Integr. Syst.
Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, Sung Kyu Lim
2014 Misc conf
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells.
VTS
Woongrae Kim, Linda Milor
2013 J jnl
A Delay Evaluation Circuit for Analog BIST Function.
IEICE Trans. Electron.
Zhengliang Lv, Shiyuan Yang, Hong Wang, Linda Milor
2013 J jnl
Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis.
Microelectron. Reliab.
Chang-Chih Chen, Fahad Ahmed, Linda Milor
2013 A conf
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms.
DATE
Chang-Chih Chen, Linda Milor
2013 — conf
System-level modeling and reliability analysis of microprocessor systems.
IWASI
Chang-Chih Chen, Linda Milor
2012 C conf
A comparative study of wearout mechanisms in state-of-art microprocessors.
ICCD
Chang-Chih Chen, Fahad Ahmed, Linda Milor
2012 J jnl
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Fahad Ahmed, Linda Milor
2012 J jnl
Backend dielectric reliability simulator for microprocessor system.
Microelectron. Reliab.
Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, Linda Milor
2012 B conf
Impact of NBTI on analog components.
ETS
Zhengliang Lv, Linda Milor, Shiyuan Yang
2012 — conf
Wearout-aware compiler-directed register assignment for embedded systems.
ISQED
Fahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor
2011 J jnl
Impact of irregular geometries on low-k dielectric breakdown.
Microelectron. Reliab.
Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim
2010 Misc conf
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST.
VTS
Fahad Ahmed, Linda Milor
2010 J jnl
Via wearout detection with on-chip monitors.
Microelectron. J.
Fahad Ahmed, Linda Milor
2009 J jnl
A DLL Design for Testing I/O Setup and Hold Times.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng Jia, Linda Milor
2009 J jnl
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements.
IEEE Des. Test Comput.
Muhammad Bashir, Linda Milor
2007 J jnl
Backend dielectric breakdown dependence on linewidth and pattern density.
Microelectron. Reliab.
Linda Milor, Changsoo Hong
2007 J jnl
Modeling of the breakdown mechanisms for porous copper/low-k process flows.
Microelectron. Reliab.
Changsoo Hong, Linda Milor
2004 J jnl
Analysis of the layout impact on electric fields in interconnect structures using finite element method.
Microelectron. Reliab.
Changsoo Hong, Linda Milor, M. Z. Lin
2002 J jnl
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
2000 A conf
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
ICCAD
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
1990 A conf
Computing Parametric Yield Accurately and Efficiently.
ICCAD
Linda Milor, Alberto L. Sangiovanni-Vincentelli
1990 A conf
Optimal Test Set Design for Analog Circuits.
ICCAD
Linda Milor, Alberto L. Sangiovanni-Vincentelli