Lih-Yih Chiou

42 papers A 2C 10Misc 1Journal 16Unranked 13
YearRankTypeTitle / Venue / Authors
2024 — conf
An Effective Neural Network Model Protection Method Against Model Stealing Attacks for Image Classification Applications.
ISOCC
Lih-Yih Chiou, Yu-Hung Lee, Chung-Chieh Chiu, Shun-Hsiu Hsu
2024 C conf
Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator.
ISCAS
Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Zu-Cheng Sheng, Soon-Jyh Chang
2024 — conf
Fast Performance and Power Profiler for SRAM Compute-in-Memory-based Accelerators.
ISOCC
Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Tzung-Jin Tsai
2021 — conf
A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique.
VLSI-DAT
Lih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li, Chen-Chung Tsai
2021 J jnl
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Chi-Ray Huang, Lih-Yih Chiou
2019 C conf
A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units.
ISCAS
Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang
2019 C conf
A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance.
ISCAS
Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei
2019 — conf
A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs.
VLSI-DAT
Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling
2019 — conf
Intelligent Policy Selection for GPU Warp Scheduler.
AICAS
Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang
2018 — conf
Fast Steady-State Thermal Analysis.
ISOCC
Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu
2018 J jnl
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F
IEEE Trans. Circuits Syst. II Express Briefs
Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, Shyh-Shyuan Sheu
2018 J jnl
Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level.
IET Cyper-Phys. Syst.: Theory & Appl.
Liang-Ying Lu, Tsung-Yu Hsieh, Pei-En Weng, Lih-Yih Chiou
2018 J jnl
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation.
IET Circuits Devices Syst.
Chi-Ray Huang, Lih-Yih Chiou
2018 J jnl
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang-Ying Lu, Lih-Yih Chiou
2018 C conf
Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme.
ISCAS
Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou
2017 C conf
A novel clock-pulse-width calibration technique for charge redistribution DACs.
ISCAS
Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Lih-Yih Chiou, Shuenn-Yuh Lee
2017 J jnl
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits.
IET Comput. Digit. Tech.
Liang-Ying Lu, Lih-Yih Chiou
2017 A conf
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches.
ISLPED
Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
2016 C conf
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors.
ISCAS
Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
2016 — conf
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
ASP-DAC
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
2016 J jnl
Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Tsai-Kan Chien, Lih-Yih Chiou, Shyh-Shyuan Sheu, Jing-Cian Lin, Chang-Chia Lee, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
2016 — conf
Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture.
APCCAS
Tsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
2015 — conf
An effective matrix compression method for GPU-accelerated thermal analysis.
VLSI-DAT
Lih-Yih Chiou, Liang-Ying Lu, Chieh-Yu Lin
2014 C conf
A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits.
ISCAS
Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu
2014 — conf
An ultra-low-power adaptive-body-bias control for subthreshold circuits.
VLSI-DAT
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
2012 — conf
Buffer size minimization method considering mix-clock domains and discontinuous data access.
APCCAS
Lih-Yih Chiou, Liang-Ying Lu, Bo-Chi Lin, Alan P. Su
2012 C conf
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.
ISCAS
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
2011 — conf
A fast and effective dynamic trace-based method for analyzing architectural performance.
ASP-DAC
Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang
2010 J jnl
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing.
IEEE Trans. Circuits Syst. II Express Briefs
Shien-Chun Luo, Lih-Yih Chiou
2010 J jnl
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst.
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2009 J jnl
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.
IEEE Trans. Very Large Scale Integr. Syst.
Lih-Yih Chiou, Shien-Chun Luo
2009 J jnl
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lih-Yih Chiou, Yi-Siou Chen, Chih-Hsien Lee
2007 C conf
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.
ISCAS
Lih-Yih Chiou, Shien-Chun Luo
2006 J jnl
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique.
IEEE J. Solid State Circuits
Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen
2006 J jnl
Crosstalk-insensitive via-programming ROMs using content-aware design framework.
IEEE Trans. Circuits Syst. II Express Briefs
Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen
2006 C conf
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.
ISCAS
Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang
2005 J jnl
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst.
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2004 — conf
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
ICASSP (5)
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2003 A conf
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
DATE
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2002 J jnl
Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
2001 Misc conf
DSP data path synthesis for low-power applications.
ICASSP
Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy
2001 J jnl
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.
VLSI Design
Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy