Lide Duan

30 papers A* 1A 2B 3C 2Misc 2Journal 12Unranked 8
YearRankTypeTitle / Venue / Authors
2022 — conf
184QPS/W 64Mb/mm
ISSCC
Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
2020 J jnl
Computer comparisons in the presence of performance variation.
Frontiers Comput. Sci.
Samuel Irving, Bin Li, Shaoming Chen, Lu Peng, Weihua Zhang, Lide Duan
2020 J jnl
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks.
CoRR
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
2020 J jnl
iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration.
IEEE Trans. Parallel Distributed Syst.
Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Xuehai Qian, Lide Duan
2019 A conf
CSOD: Context-Sensitive Overflow Detection.
CGO
Hongyu Liu, Sam Silvestro, Xiaoyin Wang, Lide Duan, Tongping Liu
2019 — conf
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification.
ASAP
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
2019 — conf
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks.
IGSC
Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan
2019 J jnl
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Armin Haj Aboutalebi, Ethan C. Ahn, Bo Mao, Suzhen Wu, Lide Duan
2018 A conf
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration.
ICS
Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Lide Duan
2018 — conf
Designing and evaluating hybrid storage for high performance cloud computing.
SysCon
Swanand Mhalagi, Lide Duan, Paul Rad
2018 C conf
Efficient Allocation and Heterogeneous Composition of NVM Crossbar Arrays for Deep Learning Acceleration.
IPCCC
Hao Yan, Armin Haj Aboutalebi, Lide Duan
2018 J jnl
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Mao, Suzhen Wu, Lide Duan
2017 Misc conf
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress.
CASES
Hao Yan, Ethan C. Ahn, Lide Duan
2017 Misc conf
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress.
CASES
Armin Haj Aboutalebi, Lide Duan
2017 J jnl
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embed. Comput. Syst.
Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin, Eugene John
2017 C conf
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance.
ICCD
Armin Haj Aboutalebi, Lide Duan
2016 — conf
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.
ASP-DAC
Lei Jiang, Wujie Wen, Danghui Wang, Lide Duan
2015 J jnl
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors.
Microprocess. Microsystems
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan
2015 B conf
Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals.
CLOUD
Lide Duan, Dongyuan Zhan, Justin Hohnerlein
2014 J jnl
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules.
IEEE Trans. Computers
Lide Duan, Ying Zhang, Bin Li, Lu Peng
2014 J jnl
Design configuration selection for hard-error reliable processors via statistical rules.
Microprocess. Microsystems
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Xin Fu
2014 — conf
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors.
ISQED
Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan
2013 J jnl
Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing.
IEEE Trans. Dependable Secur. Comput.
Lide Duan, Lu Peng, Bin Li
2012 — conf
Optimal microarchitectural design configuration selection for processor hard-error reliability.
ISQED
Ying Zhang, Lide Duan, Bin Li, Lu Peng
2011 — conf
Two-level soft error vulnerability prediction on SMT/CMP architectures.
IISWC
Lide Duan, Lu Peng, Bin Li
2011 B conf
Universal rules guided design parameter selection for soft error resilient processors.
ISPASS
Lide Duan, Ying Zhang, Bin Li, Lu Peng
2010 J jnl
Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions.
IEEE Trans. Computers
Bin Li, Lide Duan, Lu Peng
2010 J jnl
Expediating IP lookups with reduced power via TBM and SST supernode caching.
Comput. Commun.
Ying Zhang, Lu Peng, Wencheng Lu, Lide Duan, Suresh Rai
2009 A* conf
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics.
HPCA
Lide Duan, Bin Li, Lu Peng
2007 B conf
Power Efficient IP Lookup with Supernode Caching.
GLOBECOM
Lu Peng, Wencheng Lu, Lide Duan