Liangjian Lyu

26 papers C 9Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2026 — conf
A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling.
ISSCC
Jiaqing Rui, Liangjian Lyu, Yuting Wan, Kexin Shan, Wenxian Gu, C.-J. Richard Shi, Xing Wu
2025 C conf
A 0.473 μJ/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction.
ISCAS
Wenxian Gu, Xudong Hao, Hengchang Bi, Xing Wu, C.-J. Richard Shi, Liangjian Lyu
2025 J jnl
A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity.
IEEE J. Solid State Circuits
Heyu Ren, Liangjian Lyu, Binbin Chen, Wenjun Gong, Xing Wu, Chuanjin Richard Shi
2025 C conf
A 240-mV 33.8-μV/°C 1.5-nW Voltage Detector for Energy Harvesting.
ISCAS
Wenjun Gong, Binbin Chen, Liangjian Lyu, C.-J. Richard Shi
2025 C conf
A 40µW 915MHz Receiver with Sub-Passive Third-Harmonic Mixer Achieving -88dBm Sensitivity and Multi-Channel Selection.
ISCAS
Binbin Chen, Heyu Ren, Wenjun Gong, Sirou Li, Liangjian Lyu, C.-J. Richard Shi
2025 C conf
A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity.
ISCAS
Binbin Chen, Heyu Ren, Wenjun Gong, Liangjian Lyu, Chuanjin Richard Shi
2025 C conf
A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N.
ISCAS
Sirou Li, Weijia Zeng, Kaiyun Cao, Liangjian Lyu, Chuanjin Richard Shi
2025 J jnl
An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOM
IEEE Trans. Circuits Syst. I Regul. Pap.
Sirou Li, Rongjin Xu, Weijia Zeng, Kaiyun Cao, Heyu Ren, Xing Wu, Liangjian Lyu, C.-J. Richard Shi
2024 — conf
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR.
CICC
Heyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi
2023 C conf
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
ISCAS
Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu
2023 — conf
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction.
A-SSCC
Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, Chuanjin Richard Shi
2023 — conf
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF.
ESSCIRC
Renze Gan, Liangjian Lyu, Chuanjin Richard Shi
2023 — conf
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces.
ASICON
Qingzhen Wang, Wenxian Gu, Hengchang Bi, Liangjian Lyu, Deli Qiao, Xing Wu
2023 — conf
Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes.
IRPS
Zijian Zhang, Q. Li, Zuoyuan Dong, Wanting Wang, S. T. Lai, Xin Yang, Fang Liang, Chaolun Wang, C. Luo, Liangjian Lyu, Z. Li, J. M. Xu, Xing Wu
2022 — conf
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range.
CICC
Renze Gan, Liangjian Lyu, Geng Mu, Chuanjin Richard Shi
2022 J jnl
Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip.
Sensors
Haohan Wangxu, Liangjian Lyu, Hengchang Bi, Xing Wu
2021 — conf
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
CICC
Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, Chuanjin Richard Shi
2020 J jnl
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback.
Integr.
Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2020 J jnl
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst.
Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2020 C conf
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
ISCAS
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi
2020 J jnl
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi
2020 J jnl
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits
Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, Chuanjin Richard Shi
2019 C conf
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
ISCAS
Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi
2019 C conf
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
ISCAS
Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2019 — conf
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
ASP-DAC
Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2018 — conf
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
ISSCC
Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi