Liang Qi - RankMe

63 papers C 10Journal 28Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 6.4-GS/s, 200-MHz BW 77.3-dB DR 71.5-dB SNDR 2× TI Extrapolated CT DSM Employing Broadband Hybrid-Inputs Adder and Nonlinearity-Suppression DAC Encoder. IEEE J. Solid State Circuits Yuekai Liu, Yichen Jin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Zhichao Tan, Guoxing Wang, Liang Qi
2026	J	`jnl`	Analysis and Design of a Pipelined MASH Continuous-Time Delta-Sigma Modulator With 15.4 MHz-BW and 82.6 dB-SNDR. IEEE Trans. Circuits Syst. I Regul. Pap. Xinyu Qin, Yichen Jin, Mingqiang Guo, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi
2025	—	`conf`	A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. CICC Haoyu Li, Boyang Wang, Hongjiang Chen, Sai-Weng Sin, Yutao Peng, Xizhu Peng, He Tang, Chao Fan, Liang Qi, Rui Paulo Martins, Mingqiang Guo
2025	J	`jnl`	A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. IEEE J. Solid State Circuits Ke Li, Haoyu Gong, Xianyu Congzhou, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin
2025	J	`jnl`	A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. IEEE Trans. Circuits Syst. I Regul. Pap. Ran Zhang, Xueru Cen, Ka-Fai Un, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2025	J	`jnl`	A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition. IEEE J. Solid State Circuits Jieyu Li, Weifeng He, Bo Zhang, Chuxiong Lin, Liang Qi, Dingxuan Liu, Mingoo Seok
2025	J	`jnl`	A 98.7/97.5 dB-DR 10/20 kHz-BWs Dual-Mode Continuous-Time Delta-Sigma ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Kaiquan Chen, Biao Wang, Yuhan Pan, Zhichao Tan, Guoxing Wang, Yong Lian, Liang Qi
2025	J	`jnl`	An LTPS-TFT-Based Large-Area PPG Readout Circuits With Improved Linearity and Robustness for Flexible Healthcare Ring. IEEE J. Solid State Circuits Hanbo Zhang, Zhouchen Ma, Yuqing Lou, Yang Bo, Hao Wu, Liang Qi, Yongfu Li, Xiaojun Guo, Guoxing Wang, Jian Zhao
2024	—	`conf`	A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. CICC Xinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi
2024	—	`conf`	A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. CICC Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin
2024	—	`conf`	A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS. A-SSCC Yuekai Liu, Meng Guo, Yichen Jin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Zhichao Tan, Liang Qi
2024	C	`conf`	A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. ISCAS Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin
2024	—	`conf`	A TFT-Based Flexible PPG Acquisition Circuit in a 3-μm LTPS Process for Packaging-Free Smart Ring Applications. A-SSCC Hanbo Zhang, Yuqing Lou, Yang Bo, Zhouchen Ma, Hao Wu, Liang Qi, Yongfu Li, Xiaojun Guo, Guoxing Wang, Jian Zhao
2024	J	`jnl`	An Energy-Efficient FD-fNIRS Readout Circuit Employing a Mixer-First Analog Frontend and a $\Sigma$-$\Delta$ Phase-to-Digital Converter. IEEE Trans. Biomed. Circuits Syst. Zhouchen Ma, Cheng Chen, Yuxiang Lin, Liang Qi, Yongfu Li, Xia Bi, Mohamad Sawan, Guoxing Wang, Jian Zhao
2024	C	`conf`	Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM. ISCAS Meng Guo, Yuekai Liu, Jinlei Pan, Liang Qi
2024	—	`conf`	Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. ICTA Ran Zhang, Ka-Fai Un, Zhensheng Li, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2023	J	`jnl`	A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Trans. Circuits Syst. I Regul. Pap. Gaofeng Tan, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	J	`jnl`	A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. IEEE Trans. Circuits Syst. I Regul. Pap. Mingqiang Guo, Liang Qi, Weibing Zhao, Gang Xiao, Rui Paulo Martins, Sai-Weng Sin
2023	J	`jnl`	A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. IEEE J. Solid State Circuits Shulin Zhao, Mingqiang Guo, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins, Sai-Weng Sin
2023	—	`conf`	A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End. ASICON Yuekai Liu, Jinlei Pan, Liang Qi
2023	J	`jnl`	A Re-Configurable Body Channel Transceiver Towards Wearable and Flexible Biomedical Sensor Networks. IEEE Trans. Biomed. Circuits Syst. Tao He, Jing Luo, Zhen Kong, Xu Liang, Longyang Lin, Bo Zhao, Liang Qi, Yongfu Li, Guoxing Wang, Jian Zhao
2023	J	`jnl`	A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	C	`conf`	A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling. ISCAS Qingxun Wang, Yuhan Pan, Kaiquan Chen, Yu Lin, Biao Wang, Liang Qi
2023	J	`jnl`	A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs Kaiquan Chen, Biao Wang, Yan Liu, Fan Ye, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	C	`conf`	A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting. ISCAS Yuhan Pan, Qingxun Wang, Kaiquan Chen, Bin Cai, Jiuchao Qian, Yong Lian, Liang Qi
2023	—	`conf`	A Zoom Architecture Using Linear-Exponential Incremental ADC. NEWCAS Qingxun Wang, Kaiquan Chen, Liang Qi
2023	J	`jnl`	Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery. IEEE Trans. Circuits Syst. I Regul. Pap. Huaiyu Liu, Yang Lin, Liang Qi, Yongwei Lou, Guoxing Wang, Yan Liu
2023	—	`conf`	CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. ISSCC Jieyu Li, Weifeng He, Bo Zhang, Liang Qi, Guanghui He, Mingoo Seok
2023	J	`jnl`	On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi
2023	—	`conf`	Weightings in Incremental ADCs: A Tutorial Review. CICC Ruiqi Gao, Mingqiang Guo, Sai-Weng Sin, Liang Qi, Biao Wang, Guoxing Wang, Rui Paulo Martins
2022	—	`conf`	A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. CICC Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, Rui Paulo Martins
2022	J	`jnl`	A 124 dB dynamic range sigma-delta modulator applied to non-invasive EEG acquisition using chopper-modulated input-scaling-down technique. Sci. China Inf. Sci. Kaiquan Chen, Mingyi Chen, Longlong Cheng, Liang Qi, Guoxing Wang, Yong Lian
2022	J	`jnl`	A Hybrid 1 IEEE Trans. Circuits Syst. II Express Briefs Huaiyu Liu, Tongtong Guo, Peng Yan, Liang Qi, Mingyi Chen, Guoxing Wang, Yan Liu
2022	C	`conf`	A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. ISCAS Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins
2022	—	`conf`	A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture. ESSCIRC Cheng Chen, Zhouchen Ma, Yaxin Liu, Zhenhong Liu, Linfeng Zhou, Yan Wu, Liang Qi, Yongfu Li, Mohamad Sawan, Guoxing Wang, Jian Zhao
2022	J	`jnl`	A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface. IEEE Trans. Circuits Syst. II Express Briefs Huaiyu Liu, Liang Qi, Guoxing Wang, Yan Liu
2022	J	`jnl`	Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs Mingqiang Guo, Sai-Weng Sin, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins
2022	J	`jnl`	Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique. IEEE Trans. Instrum. Meas. Jiajie Huang, Ting Zhou, Huaiyu Liu, Liang Qi, Yan Liu, Yongfu Li
2022	J	`jnl`	Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs Liang Qi, Yuekai Liu, Sai-Weng Sin, Xinpeng Xing, Guoxing Wang, Maurits Ortmanns, Rui Paulo Martins
2021	C	`conf`	A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit. ISCAS Weifu Chen, Mingyi Chen, Yuzhi Hao, Liang Qi, Jian Zhao
2021	—	`conf`	A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS. ICTA Tao He, Zhen Kong, Xu Liang, Jing Luo, Longyang Lin, Liang Qi, Yongfu Li, Jian Zhao, Guoxing Wang
2021	C	`conf`	A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage. ISCAS Jiliang Zhang, Gaofeng Tan, Yue Hu, Jian Zhao, Mingyi Chen, Yongfu Li, Liang Qi
2021	J	`jnl`	A Time-Interleaved 2 IEEE J. Solid State Circuits Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins
2021	J	`jnl`	A power-efficient and re-configurable analog artificial neural network classifier. Microelectron. J. Ahmed Reda Mohamed, Liang Qi, Guoxing Wang
2021	—	`conf`	Advances in Continuous-time MASH ΔΣ Modulators. ASICON Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang
2021	—	`conf`	An Adaptively-controlled High-efficiency Buck Converter with Wide Dynamic Range for IoT Applications. ICTA Zhuo Gao, Mingyi Chen, Liang Qi, Yongfu Li, Jun Yan
2021	C	`conf`	An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V. ISCAS Ce Ma, Yuxin Ji, Cai Qiao, Ting Zhou, Liang Qi, Yongfu Li
2021	J	`jnl`	An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique. IEEE Access Chao Wang, Yuxin Ji, Ce Ma, Qiao Cai, Liang Qi, Yongfu Li
2021	—	`conf`	Continuous-time Delta-Sigma Modulators: Single-loop versus MASH. ISOCC Liang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang
2021	C	`conf`	Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. ISCAS Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang
2021	—	`conf`	Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling. ICTA Yue Hu, Jingying Zhang, Yang Zhao, Mingyi Chen, Liang Qi
2021	—	`conf`	Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review. ISOCC Mingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan
2021	—	`conf`	Low-Hardware-Cost SNN employing FeFET-based Neurons with Tunable Leaky Effect. BioCAS Hongyi Liu, Xiangao Qi, Yuqing Lou, Liang Qi, Zuo-Wei Yeh, Kea-Tiong Tang, Jian Zhao
2021	—	`conf`	Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren
2021	—	`conf`	Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi
2020	—	`conf`	A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2 VLSI Circuits Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins
2020	J	`jnl`	A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns
2020	J	`jnl`	A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Ahmed Reda Mohamed, Liang Qi, Yongfu Li, Guoxing Wang
2020	—	`conf`	A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage. APCCAS Gaofeng Tan, Haolin Lu, Xinyu Qin, Jiliang Zhang, Jingying Zhang, Yan Liu, Liang Qi
2019	—	`conf`	A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns
2019	—	`conf`	Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. ASICON Liang Qi, Sai-Weng Sin, Rui Paulo Martins
2018	C	`conf`	A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. ISCAS Yanquan Luo, Liang Qi, Ankesh Jain, Maurits Ortmanns
2017	J	`jnl`	A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins