Liang-Chia Cheng

17 papers A 2Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2017 J jnl
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang
2017 A conf
Thermal modeling and design on smartphones with heat pipe cooling technique.
ICCAD
Hong-Wen Chiou, Yu-Min Lee, Hsuan-Hsuan Hsiao, Liang-Chia Cheng
2016 J jnl
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi
2016 J jnl
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.
Integr.
Hui Geng, Jianming Liu, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi
2015 J jnl
Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi
2014 — conf
Incremental transient simulation of power grid.
ISPD
Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng
2014 — conf
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.
SoCC
Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu
2014 J jnl
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.
IEEE Trans. Circuits Syst. II Express Briefs
Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
2014 A conf
Variation aware optimal threshold voltage computation for on-chip noise sensors.
ICCAD
Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi
2013 — conf
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
ISSCC
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013 — conf
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
Asian Test Symposium
Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li
2013 — conf
Benchmarking for research in power delivery networks of three-dimensional integrated circuits.
ISPD
Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi
2013 — conf
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.
Asian Test Symposium
Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng
2013 — conf
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.
VLSI-DAT
Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng
2012 — conf
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.
ASP-DAC
Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi
2012 — conf
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
ISVLSI
Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi
2008 J jnl
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu