Liang-Chi Chen

23 papers A* 3A 6Misc 2Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Survey on Flash-Memory Storage Systems: A Host-Side Perspective.
ACM Trans. Storage
Jalil Boukhobza, Pierre Olivier, Wen Sheng Lim, Liang-Chi Chen, Yun-Shan Hsieh, Shin-Ting Wu, Chien-Chung Ho, Po-Chun Huang, Yuan-Hao Chang
2025 J jnl
Accelerating RNA-Seq Quantification on a Real Processing-in-Memory System.
IEEE Trans. Computers
Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang
2025 A conf
AridWalk: Efficient Graph Random Walks on a Resource-Limited Computational Storage Device.
ISLPED
Liang-Chi Chen, Chien-Chung Ho, Tei-Wei Kuo, Yuan-Hao Chang
2025 J jnl
PIM or CXL-PIM? Understanding Architectural Trade-offs Through Large-Scale Benchmarking.
CoRR
I-Ting Lee, Bao-Kai Wang, Liang-Chi Chen, Wen Sheng Lim, Da-Wei Chang, Yu-Ming Chang, Chieng-Chung Ho
2025 A* conf
PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System.
DAC
Chun-Le Yeh, Liang-Chi Chen, Chien-Chung Ho, Yu-Ming Chang, Da-Wei Chang
2024 — conf
LifeSqueezer: Increase the Tolerability of Weak Pages for Lifetime Improvement on TLC-based SSDs with the Off-the-shelf ECC.
RACS
Liang-Chi Chen, Kun-Chi Chiang, Chien-Chung Ho, Yu-Ming Chang, Chin-Chiang Pan, Yuan-Hao Chang
2023 Misc conf
Efficient Sanitization Design for LSM-based Key-Value Store over 3D MLC NAND Flash.
SAC
Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Wei-Chen Wang, Yung-Chun Li
2023 J jnl
Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash.
IEEE Trans. Computers
Wei-Chen Wang, Chien-Chung Ho, Yung-Chun Li, Liang-Chi Chen, Yu-Ming Chang
2023 A* conf
UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification.
DAC
Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang
2023 J jnl
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories.
ACM Trans. Embed. Comput. Syst.
Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho, Wei-Kuan Shih
2022 J jnl
LongPhase: an ultra-fast chromosome-scale phasing algorithm for small and large variants.
Bioinform.
Jyun-Hong Lin, Liang-Chi Chen, Shu-Chi Yu, Yao-Ting Huang
2022 — conf
RNA-seq Quantification on Processing in memory Architecture: Observation and Characterization.
NVMSA
Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Yuan-Hao Chang, Da-Wei Chang, Wei-Chen Wang, Yu-Ming Chang
2020 — conf
Applying Holo360 Video and Image Super-Resolution Generative Adversarial Networks to Virtual Reality Immersion.
HCI (1)
Chia-Hui Feng, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Wen-Cheng Hsu, Shih-Hao Lin
2020 — conf
Research on Aesthetic Perception of Artificial Intelligence Style Transfer.
HCI (38)
Chia-Hui Feng, Yu-Chun Lin, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Shih-Wei Yeh, Shih-Hao Lin
2011 A conf
Transition test bring-up and diagnosis on UltraSPARC
ITC
Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson
2009 A conf
Using transition test to understand timing behavior of logic circuits on UltraSPARC
ITC
Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu
2008 A conf
Transition Test on UltraSPARC- T2 Microprocessor.
ITC
Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen
2002 J jnl
TA-PSV - Timing Analysis for Partially Specified Vectors.
J. Electron. Test.
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001 A* conf
A New Gate Delay Model for Simultaneous Switching and Its Applications.
DAC
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001 A conf
Crosstalk test generation on pseudo industrial circuits: a case study.
ITC
Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
2000 — conf
A new framework for static timing analysis, incremental timing refinement, and timing simulation.
Asian Test Symposium
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
1997 Misc conf
High Quality Robust Tests for Path Delay Faults.
VTS
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
1993 A conf
On-chip test generation for combinational circuits by LFSR modification.
ICCAD
Shambhu J. Upadhyaya, Liang-Chi Chen