Li Li

99 papers C 23Misc 1Journal 48Unranked 27
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 1.1 μJ/Inference Binary Spiking Neural Network Accelerator for DVS Gesture Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Congyi Sun, Xusen Zeng, Qiang Tao, Heng Zhang, Qinyu Chen, Yuxiang Fu, Li Li
2026 J jnl
An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems.
Integr.
Shize Zhou, Wenjie Fan, Siyue Li, Yongqi Xue, Shiping Li, Songfeng Deng, Jinlun Ji, Tong Cheng, Xinyu Wang, Li Li, Yuxiang Fu
2026 J jnl
Fast Modular Reduction Algorithm and Reconfigurable Domain-Specific Architecture Design Based on Generalized Mersenne Primes.
IEEE Trans. Very Large Scale Integr. Syst.
Xinyu Wang, Guoqiang He, Yilin Wang, Jun Qian, Congyi Sun, Kai Chen, Yuxiang Fu, Li Li
2025 J jnl
An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Congyi Sun, Wenqing Song, Qinyu Chen, Chenyang Dai, Yuxiang Fu, Li Li
2025 — conf
Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip.
ASP-DAC
Tong Cheng, Zirui Xu, Xinyi Li, Li Li, Yuxiang Fu
2025 J jnl
FAS-NoC: A Real-Time Fused Approximation Scheme Coordinating Communication and Computation for NoC-Based NN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Siyue Li, Chuanzhu Liu, Wenjie Fan, Heng Zhang, Chenyang Dai, Congyi Sun, Xinyu Wang, Li Li, Yuxiang Fu
2025 C conf
FPGA-Par: An Efficient Algorithm for Elegant Partitioning in Multi-FPGA Systems.
ISCAS
Hengyue Gao, Chenyang Dai, Jinlun Ji, Bin Yan, Qiyue Zhao, Jiangtao Yuan, Feng Li, Li Li, Yuxiang Fu
2025 C conf
HengNet: An Ultra-lightweight Model with Two-level Reuse Algorithm for Seizure Detection and Prediction.
ISCAS
Heng Zhang, Linxiang Wang, Wenjie Fan, Zhenglin Gu, Youbin Luo, Xingjie Zou, Chang Gao, Qinyu Chen, Yuxiang Fu, Li Li
2025 C conf
NAME: NoC-based Accelerators Mapping Exploration for High Performance DNN Inference.
ISCAS
Jinlun Ji, Hengyue Gao, Heng Zhang, Yuqi Lu, Kai He, YuLong Song, Wenjie Fan, Li Li, Yuxiang Fu
2025 J jnl
NMIX: NoC-Aware Mixed Precision Quantization for Energy-Efficient ML Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs
Xinyi Li, Eun-Bin Park, Myeongjun Lee, Wenjie Fan, Yuxiang Fu, Li Li, Youngjoo Lee
2025 — conf
Optimizing Mixed-Precision DNN Scheduling on Heterogeneous SoCs for Enhanced Robustness and Efficiency.
AICAS
YuLong Song, Qiang Tao, Jinlun Ji, Congyi Sun, Yuxiang Fu, Li Li
2024 J jnl
A General Methodology and Reconfigurable Architecture for Calculating AB-Like Functions in the Complex Field.
IEEE Trans. Circuits Syst. II Express Briefs
Ruiqi Wu, Xinyu Wang, Jie Li, Lili Cao, Guoqiang He, Yuxiang Fu, Li Li
2024 J jnl
Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning.
IEEE Trans. Computers
Yongqi Xue, Jinlun Ji, Xinming Yu, Shize Zhou, Siyue Li, Xinyi Li, Tong Cheng, Shiping Li, Kai Chen, Zhonghai Lu, Li Li, Yuxiang Fu
2024 J jnl
Communication Synchronization-Aware Arbitration Policy in NoC-Based DNN Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Wenjie Fan, Siyue Li, Lingxiao Zhu, Zhonghai Lu, Li Li, Yuxiang Fu
2024 — conf
Environmental Sound Classification Based on Multi-channel Features and Hybrid Attention.
CISP-BMEI
Guishan Liu, Shuai Zhou, Zhangjun Peng, Li Li
2024 — conf
Four-class EEG Classification for Seizure Prediction and Detection Using a Lightweight CNN-LSTM.
BioCAS
Heng Zhang, Dan Wang, Jinlun Ji, Xiaohan Xue, Congyi Sun, Xinyu Wang, Qinyu Chen, Yuxiang Fu, Li Li
2024 J jnl
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Siyue Li, Shize Zhou, Yongqi Xue, Wenjie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li, Yuxiang Fu
2024 J jnl
Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data.
IEEE Access
Wenqing Song, Sirui Shen, Congwei Xu, Yilin Wang, Xinyu Wang, Yuxiang Fu, Li Li, Zhonghai Lu
2024 — conf
TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator.
ACM Great Lakes Symposium on VLSI
Xinyi Li, Wenjie Fan, Heng Zhang, Jinlun Ji, Tong Cheng, Shiping Li, Li Li, Yuxiang Fu
2023 J jnl
A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuxiang Fu, Kai Chen, Wenqing Song, Guoqiang He, Sirui Shen, Huizheng Wang, Chuan Zhang, Li Li
2023 J jnl
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow.
IEEE Des. Test
Lingxiao Zhu, Wenjie Fan, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li, Yuxiang Fu
2023 C conf
Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation.
ISCAS
Wanyuan Hong, Hui Chen, Lianghua Quan, Yuxiang Fu, Li Li
2022 J jnl
A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation.
IEEE Trans. Circuits Syst. II Express Briefs
Qinyu Chen, Guoqiang He, Xinyuan Wang, Jin Xu, Sirui Shen, Hui Chen, Yuxiang Fu, Li Li
2022 C conf
A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography.
ISCAS
Sirui Shen, Wenqing Song, Xinyu Wang, Xinyu Shao, Yuxiang Fu, Zhonghai Lu, Li Li
2022 C conf
AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks.
ICCD
Yongqi Xue, Jinlun Ji, Xinyi Li, Siyue Li, Shize Zhou, Tong Cheng, Li Li, Yuxiang Fu
2022 J jnl
An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Congyi Sun, Haohan Sun, Jin Xu, Jianing Han, Xinyuan Wang, Xinyu Wang, Qinyu Chen, Yuxiang Fu, Li Li
2022 J jnl
Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture.
IEEE Access
Guoqiang He, Xiaoling Ding, Minghao Zhou, Bo Liu, Li Li
2022 — conf
Deep Spiking Neural Network with Ternary Spikes.
BioCAS
Congyi Sun, Qinyu Chen, Yuxiang Fu, Li Li
2022 J jnl
Huicore: A Generalized Hardware Accelerator for Complicated Functions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hui Chen, Zongguang Yu, Jin Xu, Lin Jiang, Zhonghai Lu, Yuxiang Fu, Li Li
2022 J jnl
Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ruiqi Wu, Hui Chen, Guoqiang He, Yuxiang Fu, Li Li
2022 C conf
Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks.
ISCAS
Congyi Sun, Qinyu Chen, Kai Chen, Guoqiang He, Yuxiang Fu, Li Li
2022 Misc conf
Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems.
CASES
Shize Zhou, Yongqi Xue, Siyue Li, Jinlun Ji, Tong Cheng, Li Li, Yuxiang Fu
2021 C conf
A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation.
ISCAS
Hui Chen, Ruiqi Wu, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
2021 — conf
A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers.
ISOCC
Jin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li
2021 C conf
Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes.
ISCAS
Wenqing Song, Yifei Shen, Yuxiang Fu, Chuan Zhang, Li Li
2021 C conf
Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures.
ISCAS
Qian Gao, Wenqing Song, Zhonghai Lu, Li Li, Yuxiang Fu
2021 J jnl
IPD capacitor with pseudo-symmetry for isolated differential signal transfer applications.
Microelectron. J.
Minghao Zhou, Li Li, Xiangming Fang, Rongxiang Wu
2021 — conf
LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System.
ISOCC
Tong Cheng, Haoyu Du, Li Li, Yuxiang Fu
2021 J jnl
Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hui Chen, Zongguang Yu, Yonggang Zhang, Zhonghai Lu, Yuxiang Fu, Li Li
2021 — conf
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT.
ISOCC
Heping Yang, Hui Chen, Yuxiang Fu, Li Li
2021 — conf
Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN.
ISOCC
Menghao Guo, Tong Cheng, Li Li, Yuxiang Fu
2021 J jnl
Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxiang Fu, Chuan Zhang, Wenqing Song, Qinyu Chen, Hui Chen, Minghao Zhou, Li Li
2021 J jnl
Symmetric-Mapping LUT-Based Method and Architecture for Computing X
IEEE Trans. Circuits Syst. I Regul. Pap.
Hui Chen, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
2020 C conf
A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions.
ISCAS
Hui Chen, Lin Jiang, Yuanyong Luo, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
2020 J jnl
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective.
IEEE Trans. Very Large Scale Integr. Syst.
Qinyu Chen, Yan Huang, Rui Sun, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li
2020 J jnl
Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation.
IEEE Trans. Circuits Syst.
Hui Chen, Kaifeng Cheng, Zhonghai Lu, Yuxiang Fu, Li Li
2019 — conf
ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes.
ASICON
Wenqing Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang
2019 J jnl
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li
2019 C conf
Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.
ISCAS
Yuxiang Fu, Qinyu Chen, Guoqiang He, Kai Chen, Zhonghai Lu, Chuan Zhang, Li Li
2019 J jnl
Efficient Successive Cancellation Stack Decoder for Polar Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Wenqing Song, Huayi Zhou, Kai Niu, Zaichen Zhang, Li Li, Xiaohu You, Chuan Zhang
2019 C conf
Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning.
ISCAS
Qinyu Chen, Yuxiang Fu, Kaifeng Cheng, Wenqing Song, Zhonghai Lu, Li Li, Chuan Zhang
2019 J jnl
Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Fan Feng, Qinyu Chen, Chuan Zhang
2017 J jnl
An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Jin Sha, Jun Lin
2017 — conf
Application space exploration of a multi-fabric reconfigurable system.
ASICON
Fan Feng, Li Li, Kun Wang, Feng Han, Hongbing Pan, Wei Li
2017 J jnl
Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxiang Fu, Li Li, Kun Wang, Chuan Zhang
2017 J jnl
Optimized sorting network for successive cancellation list decoding of polar codes.
IEICE Electron. Express
Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin, Yuxiang Fu, Jin Sha
2016 C conf
A high throughput belief propagation decoder architecture for polar codes.
ISCAS
Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang
2016 C conf
Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.
ISCAS
Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Feng Han, Jun Lin
2016 J jnl
An ultra-long FFT architecture implemented in a reconfigurable application specified processor.
IEICE Electron. Express
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Baoning Zhang, Guoqiang He, Jun Lin
2016 J jnl
Design and implementation of high performance matrix inversion based on reconfigurable processor.
IEICE Electron. Express
Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin
2016 J jnl
Floating-point operation based reconfigurable architecture for radar processing.
IEICE Electron. Express
Fan Feng, Li Li, Kun Wang, Feng Han, Baoning Zhang, Guoqiang He
2016 J jnl
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
Sensors
Fei Lyu, Xinfu Liu, Yinjie Ding, Eng-Huat Toh, Zhenyan Zhang, Yifan Pan, Zhen Wang, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
2015 — conf
A high performance parallel VLSI design of matrix inversion.
ASICON
Kun Wang, Li Li, Feng Han, Hongbing Pan, Fan Feng, Xiao Yu
2015 — conf
An improved FFT architecture optimized for reconfigurable application specified processor.
ASICON
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Dong Yu
2015 — conf
Exploring stacked main memory architecture for 3D GPGPUs.
ASICON
Yuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, Hongbing Pan
2015 — conf
Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.
ASICON
Yuxiang Fu, Li Li, Yuang Zhang, Hongbing Pan, Feng Han, Kun Wang
2015 J jnl
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers.
Sensors
Fei Lyu, Zhenyan Zhang, Eng-Huat Toh, Xinfu Liu, Yinjie Ding, Yifan Pan, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
2014 — conf
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
ISIC
Fei Lyu, Zhenduo Zhu, Zhenfei Lu, Li Li, Jin Sha, Hongbing Pan, Yutong Bi
2014 J jnl
A survey of memory architecture for 3D chip multi-processors.
Microprocess. Microsystems
Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, Feng Han
2014 C conf
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.
ISCAS
Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao
2013 — conf
Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC.
ICCA
Xiao Yu, Li Li, Yuang Zhang, Hongbing Pan, Shuzhuan He
2013 J jnl
Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology.
IET Circuits Devices Syst.
Yue Xu, Hongbing Pan, Shuzhuan He, Li Li
2013 — conf
Performance and power consumption analysis of memory efficient 3D network-on-chip architecture.
ICCA
Xiao Yu, Li Li, Yuang Zhang, Hongbing Pan, Shuzhuan He
2012 J jnl
A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications.
Sensors
Yue Xu, Hongbing Pan, Shuzhuan He, Li Li
2012 J jnl
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Li Li, Bo Yuan, Zhongfeng Wang, Jin Sha, Hongbing Pan, Weishan Zheng
2011 — conf
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm.
ASICON
Jiawen Wang, Li Li, Hongbing Pan, Shuzhuan He, Rong Zhang
2010 J jnl
An Efficient VLSI Architecture for Nonbinary LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010 C conf
Application-level pipelining on Hierarchical NoC.
ISCAS
Wei Yi, Hongbing Pan, Peng Pan, Li Li, Minglun Gao, Ning Hou, Gaoming Du, Duoli Zhang
2010 J jnl
Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010 J jnl
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin
2010 C conf
Layered decoding for non-binary LDPC codes.
ISCAS
Shuai Zhou, Jin Sha, Li Li, Zhongfeng Wang
2010 C conf
Low power decoder design for QC-LDPC codes.
ISCAS
Kai He, Jin Sha, Li Li, Zhongfeng Wang
2009 — conf
An improved min-sum based column-layered decoding algorithm for LDPC codes.
SiPS
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2009 J jnl
An improved scaled DCT architecture.
IEEE Trans. Consumer Electron.
Zhigang Wu, Jin Sha, Zhongfeng Wang, Li Li, Minglun Gao
2009 C conf
Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications.
ISCAS
Bo Yuan, Li Li, Jin Sha, Zhongfeng Wang
2009 J jnl
Area-efficient reed-solomon decoder design for optical communications.
IEEE Trans. Circuits Syst. II Express Briefs
Bo Yuan, Zhongfeng Wang, Li Li, Minglun Gao, Jin Sha, Chuan Zhang
2009 J jnl
Decoder Design for RS-Based LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs
Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2009 J jnl
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs
Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao
2009 — conf
High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications.
SiPS
Bo Yuan, Li Li, Zhongfeng Wang
2009 C conf
High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications.
ISCAS
Chuan Zhang, Li Li, Jun Xu, Zhongfeng Wang
2009 C conf
LDPC Decoder Design for IEEE 802.15 Standard.
ISCAS
Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang
2009 J jnl
LDPC decoder design for high rate wireless personal area networks.
IEEE Trans. Consumer Electron.
Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2009 J jnl
Multi-Gb/s LDPC Code Design and Implementation.
IEEE Trans. Very Large Scale Integr. Syst.
Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li
2009 C conf
Towards an Optimal Trade-off of Viterbi Decoder Design.
ISCAS
Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li
2008 — conf
A scalable distributed memory architecture for Network on Chip.
APCCAS
Yuang Zhang, Li Li, Shengguang Yang, Lan Dong, Xiaoxiang Lou, Minglun Gao
2008 — conf
Low-complexity shift-LDPC decoder for high-speed communication systems.
APCCAS
Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang
2008 — conf
Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System.
APCCAS
Li Li, Yong-Sheng Yin, Minglun Gao
2007 — conf
On the Implementation of Virtual Array Using Configuration Plane.
APPT
Yongsheng Yin, Li Li, Minglun Gao, Gaoming Du, Yu-Kun Song
2006 — conf
An FPGA Implementation of Array LDPC Decoder.
APCCAS
Jin Sha, Minglun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang