| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2026 | — | conf |
ASPLOS (1)
|
| 2026 | B | conf |
PPoPP
|
| 2026 | — | conf |
ASP-DAC
|
| 2026 | — | conf |
ASPLOS (2)
|
| 2026 | J | jnl |
CoRR
|
| 2026 | A* | conf |
HPCA
|
| 2026 | A* | conf |
AAAI
|
| 2026 | — | conf |
ASP-DAC
|
| 2026 | — | conf |
ASP-DAC
|
| 2025 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
DAC
|
| 2025 | J | jnl |
CoRR
|
| 2025 | — | conf |
ASPLOS (3)
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
ACM Multimedia
|
| 2025 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2025 | A* | conf |
DAC
|
| 2025 | A* | conf |
HPCA
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A | conf |
DATE
|
| 2025 | — | conf |
ASP-DAC
|
| 2025 | A* | conf |
ISCA
|
| 2025 | — | conf |
EMNLP (Findings)
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2025 | A* | conf |
HPCA
|
| 2025 | A | conf |
DATE
|
| 2025 | — | conf |
APPT
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
DAC
|
| 2025 | J | jnl |
CoRR
|
| 2025 | — | conf |
ASP-DAC
|
| 2025 | A | conf |
DATE
|
| 2025 | A | conf |
ICCAD
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A | conf |
ICCAD
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
IEEE Trans. Computers
|
| 2025 | — | conf |
APPT
|
| 2025 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2025 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A | conf |
DATE
|
| 2024 | A* | conf |
MICRO
|
| 2024 | A* | conf |
DAC
|
| 2024 | J | jnl |
ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity.
IEEE Trans. Computers
|
| 2024 | C | conf |
ICCD
|
| 2024 | J | jnl |
ACM Trans. Archit. Code Optim.
|
| 2024 | J | jnl |
IEEE Trans. Parallel Distributed Syst.
|
| 2024 | C | conf |
ICCD
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | A* | conf |
DAC
|
| 2024 | A | conf |
ISLPED
|
| 2024 | A* | conf |
ISCA
|
| 2024 | C | conf |
ICCD
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | C | conf |
ICCD
|
| 2024 | A | conf |
DATE
|
| 2024 | A* | conf |
HPCA
|
| 2024 | A* | conf |
MICRO
|
| 2024 | J | jnl |
IEEE Trans. Circuits Syst. Artif. Intell.
|
| 2024 | C | conf |
ICCD
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | B | conf |
ASPDAC
|
| 2024 | J | jnl |
CoRR
|
| 2024 | A* | conf |
ISCA
|
| 2024 | J | jnl |
IEEE Trans. Computers
|
| 2024 | — | conf |
Euro-Par (2)
|
| 2023 | — | conf |
NoCArc@MICRO
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2023 | C | conf |
ICCD
|
| 2023 | A* | conf |
DAC
|
| 2023 | A | conf |
ICCAD
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2023 | A | conf |
DATE
|
| 2023 | A | conf |
DATE
|
| 2023 | C | conf |
ICCD
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2023 | A | conf |
DATE
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2023 | A* | conf |
DAC
|
| 2022 | J | jnl |
CoRR
|
| 2022 | — | conf |
ISQED
|
| 2022 | J | jnl |
CoRR
|
| 2022 | A | conf |
DATE
|
| 2022 | A* | conf |
DAC
|
| 2022 | — | conf |
ASP-DAC
|
| 2022 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2022 | A* | conf |
SIGIR
|
| 2022 | A | conf |
FPGA
|
| 2022 | J | jnl |
IEEE Trans. Computers
|
| 2022 | J | jnl |
CoRR
|
| 2022 | A* | conf |
DAC
|
| 2022 | C | conf |
ICCD
|
| 2022 | J | jnl |
CoRR
|
| 2022 | A* | conf |
DAC
|
| 2022 | A | conf |
DATE
|
| 2022 | A* | conf |
AAAI
|
| 2021 | — | conf |
ICTA
|
| 2021 | A | conf |
CIKM
|
| 2021 | A* | conf |
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference.
DAC
|
| 2021 | J | jnl |
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference.
CoRR
|
| 2021 | J | jnl |
ACM Trans. Reconfigurable Technol. Syst.
|
| 2021 | A | conf |
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.
ICCAD
|
| 2021 | A | conf |
DATE
|
| 2021 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2021 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2021 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2021 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2021 | A* | conf |
ICCV
|
| 2021 | C | conf |
CLUSTER
|
| 2021 | J | jnl |
CoRR
|
| 2021 | Misc | conf |
VTS
|
| 2021 | A* | conf |
DAC
|
| 2021 | — | conf |
ISPA/BDCloud/SocialCom/SustainCom
|
| 2021 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2021 | C | conf |
ISCAS
|
| 2021 | C | conf |
ICCD
|
| 2021 | J | jnl |
CoRR
|
| 2021 | — | conf |
CISP-BMEI
|
| 2021 | J | jnl |
CoRR
|
| 2021 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2020 | B | conf |
FPL
|
| 2020 | J | jnl |
CoRR
|
| 2020 | A* | conf |
ISCA
|
| 2020 | — | conf |
ACM Great Lakes Symposium on VLSI
|
| 2020 | A* | conf |
DAC
|
| 2020 | A | conf |
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.
DATE
|
| 2020 | Misc | conf |
VTS
|
| 2020 | J | jnl |
IEEE Robotics Autom. Lett.
|
| 2020 | A* | conf |
DAC
|
| 2019 | — | conf |
ASP-DAC
|
| 2019 | A | conf |
ISLPED
|
| 2019 | J | jnl |
CoRR
|
| 2019 | A | conf |
DATE
|
| 2019 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2019 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2019 | — | conf |
ASP-DAC
|
| 2019 | J | jnl |
CoRR
|
| 2019 | A* | conf |
DAC
|
| 2018 | A | conf |
FPGA
|
| 2018 | J | jnl |
CoRR
|
| 2018 | A | conf |
ICCAD
|
| 2018 | J | jnl |
CoRR
|
| 2018 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2018 | J | jnl |
IEEE Trans. Parallel Distributed Syst.
|
| 2018 | A | conf |
DATE
|
| 2018 | J | jnl |
CoRR
|
| 2018 | A | conf |
ICCAD
|
| 2018 | A | conf |
DATE
|
| 2018 | J | jnl |
ACM Trans. Design Autom. Electr. Syst.
|
| 2017 | A | conf |
DATE
|
| 2017 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2017 | A | conf |
DATE
|
| 2017 | J | jnl |
Concurr. Comput. Pract. Exp.
|
| 2017 | A* | conf |
DAC
|
| 2017 | A* | conf |
DAC
|
| 2016 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2016 | C | conf |
ISPDC
|
| 2016 | C | conf |
ICCD
|
| 2016 | A* | conf |
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.
MICRO
|
| 2016 | A | conf |
ITC
|
| 2016 | J | jnl |
IEEE Trans. Computers
|
| 2015 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2015 | C | conf |
ICCD
|
| 2015 | A | conf |
ISLPED
|
| 2015 | A | conf |
ICS
|
| 2015 | — | conf |
NOCS
|
| 2015 | A* | conf |
DAC
|
| 2015 | A | conf |
ITC
|
| 2015 | — | conf |
SoCC
|
| 2015 | — | conf |
ASP-DAC
|
| 2015 | — | conf |
SoCC
|
| 2015 | A | conf |
ITC
|
| 2013 | A | conf |
ITC
|
| 2013 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2013 | A* | conf |
DAC
|
| 2012 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2012 | A | conf |
DATE
|
| 2012 | — | conf |
ASP-DAC
|
| 2010 | A | conf |
ITC
|
| 2010 | A | conf |
ICCAD
|
| 2009 | A | conf |
ICCAD
|
| 2009 | A | conf |
DATE
|