Li-Da Huang

15 papers A* 1A 3C 1Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2009 — conf
A stochastic-based efficient critical area extractor on OpenAccess platform.
ACM Great Lakes Symposium on VLSI
Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan
2008 — conf
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow.
ACM Great Lakes Symposium on VLSI
Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu
2007 — conf
OPC-Friendly Bus Driven Floorplanning.
ISQED
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
2007 — conf
Using power gating techniques in area-array SoC floorplan design.
SoCC
Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu
2005 — conf
Redundant-via enhanced maze routing for yield improvement.
ASP-DAC
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
2005 J jnl
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
2004 J jnl
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
2004 C conf
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
ICCD
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
2004 A* conf
Optical proximity correction (OPC): friendly maze routing.
DAC
Li-Da Huang, Martin D. F. Wong
2003 — conf
Explicit gate delay model for timing evaluation.
ISPD
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
2003 — conf
Floorplanning with power supply noise avoidance.
ASP-DAC
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
2003 A conf
Global Wire Bus Configuration with Minimum Delay Uncertainty.
DATE
Li-Da Huang, Hung-Ming Chen, D. F. Wong
2003 J jnl
Maze routing with buffer insertion under transition time constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
2002 A conf
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.
DATE
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
2002 A conf
Maze Routing with Buffer Insertion under Transition Time Constraints.
DATE
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao