Leonid Yavits - RankMe

83 papers A* 2B 2C 5Misc 1Journal 64Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	BinDRAM: Binary neural network on unmodified commodity DRAM. Future Gener. Comput. Syst. Dan Yaron, Benjamin Wolfzon, Zuher Jahshan, Alexander Fish, Leonid Yavits
2026	J	`jnl`	CADM: Content addressable commodity off-the-shelf DRAM-based genome classifier. J. Syst. Archit. Esteban Garzón, Alexander Fish, Leonid Yavits
2026	J	`jnl`	GainP: A Gain Cell Embedded DRAM-based associative in-memory processor. J. Syst. Archit. Yaniv Levi, Odem Harel, Adam Teman, Leonid Yavits
2026	J	`jnl`	GenMClass: Design and comparative analysis of genome classifier-on-chip platform. J. Syst. Archit. Daria Bromot, Yehuda Kra, Zuher Jahshan, Esteban Garzón, Adam Teman, Leonid Yavits
2026	J	`jnl`	HardCAM: A 65 nm radhard CAM design and evaluation for space applications. Array Itay Merlin, Yuval Harary, Daniel Amar, Eyal Rechef, Avner Haran, Eran Mazal Tov, Alexander Fish, Leonid Yavits
2026	J	`jnl`	MANAR: Memory-augmented Attention with Navigational Abstract Conceptual Representation. CoRR Zuher Jahshan, Ben Ben Ishay, Leonid Yavits
2026	J	`jnl`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CoRR Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2026	J	`jnl`	SPARCAM: Sparse matrix multiplication accelerator using multi-port dynamic CAM. J. Syst. Archit. Esteban Garzón, Benjamin Zambrano, David Sheinenzon, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance. IEEE J. Solid State Circuits Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	CAM4: In-Memory Viral Pathogen Genome Classification Using Similarity Search Dynamic Content-Addressable Memory. IEEE Trans. Emerg. Top. Comput. Zuher Jahshan, Itay Merlin, Esteban Garzón, Leonid Yavits
2025	J	`jnl`	GCOC: A Genome Classifier-On-Chip Based on Similarity Search Content Addressable Memory. IEEE Trans. Biomed. Circuits Syst. Yuval Harary, Paz Snapir, Shir Siman Tov, Chen Kruphman, Eyal Rechef, Zuher Jahshan, Esteban Garzón, Leonid Yavits
2025	—	`conf`	KSPiM: A 65nm Processing-near-Memory State-Space Accelerator for Keyword Spotting. CCMCC Almog Sharoni, Zuher Jahshan, Yehuda Kra, Adam Teman, Leonid Yavits
2025	—	`conf`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CCMCC Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	Processing-in-memory for genomics workloads. CoRR William Andrew Simon, Leonid Yavits, Konstantina Koliogeorgi, Yann Falevoz, Yoshihiro Shibuya, Dominique Lavenier, Irem Boybat, Klea Zambaku, Berkan Sahin, Mohammad Sadrosadati, Onur Mutlu, Abu Sebastian, Rayan Chikhi, The BioPIM Consortium, Can Alkan
2025	J	`jnl`	SpaceCAM: A 16 nm FinFET Low-Power Soft-Error Tolerant TCAM Design for Space Communication Applications. IEEE Access Itay Merlin, Benjamin Zambrano, Marco Lanuzza, Alexander Fish, Avner Haran, Leonid Yavits
2025	C	`conf`	Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. ISCAS Ramiro Taco, Esteban Garzón, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	CoNfasTT: A Configurable, Scalable, and Fast Dual Mode Logic-Based NTT Design. IEEE Access Eldar Cohen, Leonid Yavits, Benjamin M. Zaidel, Alexander Fish, Itamar Levi
2024	J	`jnl`	DIPER: Detection and Identification of Pathogens Using Edit Distance-Tolerant Resistive CAM. IEEE Trans. Computers Itay Merlin, Esteban Garzón, Alexander Fish, Leonid Yavits
2024	J	`jnl`	DRAMA: Commodity DRAM Based Content Addressable Memory. IEEE Comput. Archit. Lett. Leonid Yavits
2024	J	`jnl`	Designing Precharge-Free Energy-Efficient Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. Ramiro Taco, Esteban Garzón, Robert Hanhan, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
2024	—	`conf`	Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. PRIME Netanel Shavit, Inbal Stanger, Ramiro Taco, Leonid Yavits, Alexander Fish
2024	J	`jnl`	MajorK: Majority Based kmer Matching in Commodity DRAM. IEEE Comput. Archit. Lett. Zuher Jahshan, Leonid Yavits
2024	J	`jnl`	ViRAL: Vision Transformer Based Accelerator for ReAL Time Lineage Assignment of Viral Pathogens. IEEE Access Zuher Jahshan, Esteban Garzón, Leonid Yavits
2024	J	`jnl`	ViTAL: Vision TrAnsformer based Low coverage SARS-CoV-2 lineage assignment. Bioinform. Zuher Jahshan, Leonid Yavits
2023	J	`jnl`	A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
2023	J	`jnl`	AM IEEE J. Emerg. Sel. Topics Circuits Syst. Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023	J	`jnl`	ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky
2023	A*	`conf`	DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification. MICRO Zuher Jahshan, Itay Merlin, Esteban Garzón, Leonid Yavits
2023	J	`jnl`	DRAMA: Commodity DRAM based Content Addressable Memory. CoRR Leonid Yavits
2023	—	`conf`	STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
2022	J	`jnl`	AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	J	`jnl`	CoViT: Real-time phylogenetics for the SARS-CoV-2 pandemic using Vision Transformers. CoRR Zuher Jahshan, Leonid Yavits
2022	A*	`conf`	EDAM: edit distance tolerant approximate matching content addressable memory. ISCA Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	J	`jnl`	FiltPIM: In-Memory Filter for DNA Sequencing. CoRR Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2022	J	`jnl`	GIRAF: General Purpose In-Storage Resistive Associative Framework. IEEE Trans. Parallel Distributed Syst. Leonid Yavits, Roman Kaplan, Ran Ginosar
2022	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2021	—	`conf`	FiltPIM: In-Memory Filter for DNA Sequencing. ICECS Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2021	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2020	Misc	`conf`	BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. SYSTOR Roman Kaplan, Leonid Yavits, Ran Ginosar
2020	C	`conf`	Dual Mode Logic Address Decoder. ISCAS Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish
2020	C	`conf`	Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
2020	C	`conf`	Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
2020	C	`conf`	WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. ICCD Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
2020	J	`jnl`	WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. CoRR Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
2019	J	`jnl`	AIDA: Associative DNN Inference Accelerator. CoRR Leonid Yavits, Roman Kaplan, Ran Ginosar
2019	J	`jnl`	BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar
2019	B	`conf`	POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. PACT Roman Kaplan, Leonid Yavits, Ran Ginosar
2019	B	`conf`	POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. PACT Leonid Yavits, Roman Kaplan, Ran Ginosar
2019	J	`jnl`	RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. IEEE Micro Roman Kaplan, Leonid Yavits, Ran Ginosar
2018	J	`jnl`	Accelerator for Sparse Machine Learning. IEEE Comput. Archit. Lett. Leonid Yavits, Ran Ginosar
2018	J	`jnl`	Enabling Full Associativity with Memristive Address Decoder. IEEE Micro Leonid Yavits, Roman Kaplan, Ran Ginosar
2018	J	`jnl`	PRINS: Resistive CAM Processing in Storage. CoRR Leonid Yavits, Roman Kaplan, Ran Ginosar
2018	J	`jnl`	RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	Cache Hierarchy Optimization. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2017	J	`jnl`	From Processing-in-Memory to Processing-in-Storage. Supercomput. Front. Innov. Roman Kaplan, Leonid Yavits, Ran Ginosar
2017	J	`jnl`	MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar
2017	J	`jnl`	Resistive Address Decoder. IEEE Comput. Archit. Lett. Leonid Yavits, Uri C. Weiser, Ran Ginosar
2017	J	`jnl`	Sparse Matrix Multiplication On An Associative Processor. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2017	J	`jnl`	Sparse Matrix Multiplication on CAM Based Accelerator. CoRR Leonid Yavits, Ran Ginosar
2017	J	`jnl`	The Effect of Temperature on Amdahl Law in 3D Multicore Era. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2016	J	`jnl`	Convex Optimization of Real Time SoC. CoRR Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser
2016	—	`conf`	Deduplication in resistive content addressable memory based solid state drive. PATMOS Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar
2016	J	`jnl`	Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2016	J	`jnl`	Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar
2016	J	`jnl`	The Effect of Temperature on Amdahl Law in 3D Multicore Era. IEEE Trans. Computers Leonid Yavits, Amir Morad, Ran Ginosar
2015	J	`jnl`	Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Computers Leonid Yavits, Amir Morad, Ran Ginosar
2015	J	`jnl`	Resistive Associative Processor. IEEE Comput. Archit. Lett. Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar
2015	J	`jnl`	Sparse Matrix Multiplication On An Associative Processor. IEEE Trans. Parallel Distributed Syst. Leonid Yavits, Amir Morad, Ran Ginosar
2014	J	`jnl`	Cache Hierarchy Optimization. IEEE Comput. Archit. Lett. Leonid Yavits, Amir Morad, Ran Ginosar
2014	—	`conf`	Convex optimization of resource allocation in asymmetric and heterogeneous SoC. PATMOS Amir Morad, Leonid Yavits, Ran Ginosar
2014	—	`conf`	Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. PATMOS Amir Morad, Leonid Yavits, Ran Ginosar
2014	J	`jnl`	GP-SIMD Processing-in-Memory. ACM Trans. Archit. Code Optim. Amir Morad, Leonid Yavits, Ran Ginosar
2014	J	`jnl`	Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2014	J	`jnl`	The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Comput. Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	3D Cache Hierarchy Optimization. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2013	—	`conf`	3D cache hierarchy optimization. 3DIC Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	Thermal analysis of 3D associative processor. CoRR Leonid Yavits, Amir Morad, Ran Ginosar