Leonardo Rezende Juracy

17 papers A 1C 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
Deploying human activity recognition in embedded RISC-V processors.
Des. Autom. Embed. Syst.
Willian Analdo Nunes, Rafael Schild Reusch, Lucas Luza, Eduardo Bernardon, Angelo Elias Dalzotto, Leonardo Rezende Juracy, Fernando Gehm Moraes
2023 J jnl
A Comprehensive Evaluation of Convolutional Hardware Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Leonardo Rezende Juracy, Alexandre M. Amory, Fernando Moraes
2023 — conf
Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition.
SBESC
Rafael Schild Reusch, Leonardo Rezende Juracy, Fernando Gehm Moraes
2023 J jnl
From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks.
Found. Trends Electron. Des. Autom.
Leonardo Rezende Juracy, Rafael Garibotti, Fernando Gehm Moraes
2022 J jnl
A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Leonardo Rezende Juracy, Alexandre de Morais Amory, Fernando Gehm Moraes
2022 — —
A framework for fast architecture exploration of convolutional neural network accelerators
Leonardo Rezende Juracy
2022 — conf
Assessment and Optimization of 1D CNN Model for Human Activity Recognition.
SBESC
Rafael Schild Reusch, Leonardo Rezende Juracy, Fernando Gehm Moraes
2021 J jnl
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Alexandre F. Hampel, Fernando Gehm Moraes
2021 — conf
A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators.
LASCAS
Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes
2020 J jnl
A Survey of Aging Monitors and Reconfiguration Techniques.
CoRR
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
2020 — conf
Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template.
ASYNC
Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
2018 J jnl
A DfT Insertion Methodology to Scannable Q-Flop Elements.
IEEE Trans. Very Large Scale Integr. Syst.
Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory
2018 C conf
An LSSD Compliant Scan Cell for Flip-Flops.
ISCAS
Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory
2018 A conf
On the reuse of timing resilient architecture for testing path delay faults in critical paths.
DATE
Felipe A. Kuentzer, Leonardo Rezende Juracy, Alexandre M. Amory
2018 — conf
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.
SBCCI
Felipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory
2017 J jnl
Optimized Design of an LSSD Scan Cell.
IEEE Trans. Very Large Scale Integr. Syst.
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory
2017 — conf
XGT4: An industrial grade, open source tester for multi-gigabit networks.
ICECS
Leonardo Rezende Juracy, Felipe B. Lazzarotto, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Gehm Moraes