Leon Stok

45 papers A* 5A 12Journal 16Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
Chip Design in the Era of AI & Quantum: From Idea to IC, are we there yet?
ISPD
Leon Stok
2025 J jnl
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors.
CoRR
Nicolas Dupuis, Ravi Nair, Shyam Ramji, Sean McClintock, Nishant Chauhan, Priyanka Nagpal, Bart Blaner, Ken Valk, Leon Stok, Ruchir Puri
2025 A conf
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design.
ICCAD
Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov
2025 J jnl
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design.
CoRR
Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov
2023 — conf
Quantum Challenges for EDA.
ISPD
Leon Stok
2021 — conf
EDA and Quantum Computing: The key role of Quantum Circuits.
ISPD
Leon Stok
2021 J jnl
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology.
IEEE Des. Test
Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon
2020 J jnl
EDA and Quantum Computing: a symbiotic relationship?
IEEE Des. Test
Shesha Raghunathan, Leon Stok
2018 — conf
Concurrent High Performance Processor Design: From Logic to PD in Parallel.
ISPD
Leon Stok
2018 — ch.
EDA3.0: Implications to Logic Synthesis.
Advanced Logic Synthesis
Leon Stok
2014 J jnl
The Next 25 Years in EDA: A Cloudy Future?
IEEE Des. Test
Leon Stok
2013 J jnl
Developing Parallel EDA Tools [The Last Byte].
IEEE Des. Test
Leon Stok
2011 A* ed.
Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011
DAC
Leon Stok, Nikil D. Dutt, Soha Hassoun
2010 A* conf
EDA challenges and options: investing for the future.
DAC
Ruchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok
2009 — conf
From restrictive to prescriptive design.
ASP-DAC
Leon Stok
2008 J jnl
Variability and New Design Paradigms.
IEEE Des. Test Comput.
Leon Stok
2007 J jnl
DAC Highlights.
IEEE Des. Test Comput.
Sachin S. Sapatnekar, Leon Stok
2005 A* conf
Keeping hot chips cool.
DAC
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
2005 — conf
Minimizing power with flexible voltage islands.
ISCAS (1)
Ruchir Puri, David S. Kung, Leon Stok
2003 J jnl
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Soha Hassoun, Steven M. Nowick, Leon Stok
2003 A* conf
Pushing ASIC performance in a power envelope.
DAC
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
2003 — conf
There is life left in ASICs.
ISPD
Leon Stok, John M. Cohn
2002 A conf
Layout Driven Decomposition with Congestion Consideration.
DATE
Thomas Kutzschebauch, Leon Stok
2001 A conf
Congestion Aware Layout Driven Logic Synthesis.
ICCAD
Thomas Kutzschebauch, Leon Stok
2000 J jnl
Combinatorial cell design for CMOS libraries.
Integr.
Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok
2000 A conf
Regularity Driven Logic Synthesis.
ICCAD
Thomas Kutzschebauch, Leon Stok
2000 — conf
Timing closure: the solution and its problems.
ASP-DAC
Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
2000 A conf
Transformational Placement and Synthesis.
DATE
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
1999 A conf
Wavefront Technology Mapping.
DATE
Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
1998 J jnl
Don't cares in synthesis: theoretical pitfalls and practical solutions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
1998 A conf
Gate-size selection for standard cell libraries.
ICCAD
Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok
1997 A conf
Timing analysis and optimization: from devices to systems (tutorial).
ICCAD
Anirudh Devgan, Leon Stok, Sandip Kundu
1996 J jnl
BooleDozer: Logic synthesis for ASICs.
IBM J. Res. Dev.
Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler
1996 J jnl
Retiming revisited and reversed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guy Even, Ilan Y. Spillinger, Leon Stok
1995 A conf
Be careful with don't cares.
ICCAD
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
1995 A conf
Efficient use of large don't cares in high-level and logic synthesis.
ICCAD
Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash
1995 J jnl
High-level synthesis in an industrial environment.
IBM J. Res. Dev.
Reinaldo A. Bergamaschi, Richard A. O'Connor, Leon Stok, Michael Z. Moricz, Shiv Prakash, Andreas Kuehlmann, D. Sreenivasa Rao
1995 — conf
Improving initialization through reversed retiming.
ED&TC
Leon Stok, Ilan Y. Spillinger, Guy Even
1994 J jnl
Data path synthesis.
Integr.
Leon Stok
1994 — conf
Is high-level synthesis marketable? (panel).
HLSS
Leon Stok
1992 A conf
False loops through resource sharing.
ICCAD
Leon Stok
1992 J jnl
Foreground memory management in data path synthesis.
Int. J. Circuit Theory Appl.
Leon Stok, Jochen A. G. Jess
1991 A conf
Flexible Block-Multiplier Generation.
ICCAD
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok
1990 — conf
Interconnect optimisation during data path allocation.
EURO-DAC
Leon Stok
1989 A* conf
From Network to Artwork.
DAC
Leon Stok, G. P. Koster