Leomar S. da Rosa Jr.

27 papers C 5Journal 7Unranked 15
YearRankTypeTitle / Venue / Authors
2023 J jnl
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.
J. Electron. Test.
Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen
2022 C conf
Fault Tolerance Evaluation of Different Majority Voter Designs.
ISCAS
Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr., Paulo F. Butzen, Rafael Iankowski Soares
2021 J jnl
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.
ACM Trans. Design Autom. Electr. Syst.
Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques
2020 J jnl
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing.
IEEE Trans. Circuits Syst. II Express Briefs
Stéphano M. M. Gonçalves, Leomar S. da Rosa Jr., Felipe de Souza Marques
2020 J jnl
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.
CoRR
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2019 C conf
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
ISCAS
Vitor G. Lima, Guilherme Paim, Leandro M. G. Rocha, Leomar S. da Rosa Jr., Felipe S. Marques, Eduardo A. C. da Costa, Vinícius V. Camargo, Rafael Soares, Sergio Bampi
2018 — conf
Area-Aware Design of Static CMOS Complex Gates.
NEWCAS
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques
2018 J jnl
Libra: An Automatic Design Methodology for CMOS Complex Gates.
IEEE Trans. Circuits Syst. II Express Briefs
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques
2018 — conf
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.
ICECS
Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen
2018 — conf
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits.
ICECS
Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco
2017 — conf
A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
ICECS
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017 C conf
A survey of path search algorithms for VLSI detailed routing.
ISCAS
Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe de Souza Marques
2017 C conf
Post-processing of supergate networks aiming cell layout optimization.
ISCAS
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2017 J jnl
Transistor Count Optimization in IG FinFET Network Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2016 — conf
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
LASCAS
Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.
2013 — conf
Improving the methodology to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2013 — conf
Transistor-level optimization of CMOS complex gates.
LASCAS
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012 — conf
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
SBCCI
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2010 C conf
Boolean factoring with multi-objective goals.
ICCD
Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis
2010 J jnl
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.
Microelectron. J.
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas
2009 — conf
Switch level optimization of digital CMOS gate networks.
ISQED
Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis
2008 — conf
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
ACM Great Lakes Symposium on VLSI
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas
2008 — conf
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
ISQED
Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis
2007 — conf
A comparative study of CMOS gates with minimum transistor stacks.
SBCCI
Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider
2007 — conf
DAG based library-free technology mapping.
ACM Great Lakes Symposium on VLSI
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2006 — conf
Fast disjoint transistor networks from BDDs.
SBCCI
Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2003 — conf
Scheduling Policy Costs on a JAVA Microcontroller.
OTM Workshops
Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis