Lennart M. Reimann

32 papers A* 1A 3C 4Misc 1Journal 17Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. ICCAD Evgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. CoRR Evgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers
2025	A*	`conf`	Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. DAC Rebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. CoRR Rebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Leveraging SystemC-TLM-based Virtual Prototypes for Embedded Software Fuzzing. CoRR Chiara Ghinami, Jonas Winzer, Nils Bosbach, Lennart M. Reimann, Lukas Jünger, Simon Wörner, Rainer Leupers
2025	J	`jnl`	Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer. CoRR Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Niklas Degener, Florian Idrizi, Lennart M. Reimann, Jan Moritz Joseph, Rainer Leupers
2025	—	`—`	Protecting confidentiality in hardware design: EDA tools for security awareness. Lennart M. Reimann
2025	A	`conf`	Static Global Register Allocation for Dynamic Binary Translators. DATE Niko Zurstraßen, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	—	`conf`	The Impact of Logic Locking on Confidentiality: An Automated Evaluation. ISQED Lennart M. Reimann, Evgenii Rezunov, Dominik Germek, Luca Collini, Christian Pilato, Ramesh Karri, Rainer Leupers
2025	J	`jnl`	The Impact of Logic Locking on Confidentiality: An Automated Evaluation. CoRR Lennart M. Reimann, Evgenii Rezunov, Dominik Germek, Luca Collini, Christian Pilato, Ramesh Karri, Rainer Leupers
2024	J	`jnl`	Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction. CoRR Lennart M. Reimann, Yadu Madhukumar Variyar, Lennet Huelser, Chiara Ghinami, Dominik Germek, Rainer Leupers
2024	J	`jnl`	QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	—	`conf`	Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. NEWCAS Lennart M. Reimann, Felix Staudigl, Rainer Leupers
2023	J	`jnl`	Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. CoRR Lennart M. Reimann, Felix Staudigl, Rainer Leupers
2023	—	`conf`	Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature. VLSI-SoC (Selected Papers) Lennart M. Reimann, Jonathan Wiesner, Karol Jaszczyk, Chiara Ghinami, Dominik Germek, Farhad Merchant, Rainer Leupers
2023	—	`conf`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2023	C	`conf`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	J	`jnl`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	A	`conf`	ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer
2022	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2022	J	`jnl`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2021	Misc	`conf`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	J	`jnl`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2021	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2021	C	`conf`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	C	`conf`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2020	C	`conf`	A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß
2020	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2020	—	`conf`	Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß