Lei Zhou - RankMe

19 papers C 1Journal 13Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, DanYu Wu, Jin Wu, Xinyu Liu
2025	J	`jnl`	A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS. IEICE Electron. Express Ben He, Xuan Guo, Hanbo Jia, Kai Sun, Lei Zhou, Zhijie Chen, Xinyu Liu
2024	J	`jnl`	A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Xing Li, Lei Zhou, Xuan Guo, Hanbo Jia, DanYu Wu, Jin Wu, Xinyu Liu
2021	—	`conf`	A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC Chen Cai, Xuqiang Zheng, Yong Chen, DanYu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu
2021	—	`conf`	A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. ESSCIRC Jian Luan, DanYu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu
2020	J	`jnl`	100 Gb/s (4 × 25 Gb/s) real-time coherent UDWDM-PON with a large power budget. JOCN Ming Luo, DanYu Wu, Weizhong Li, Tao Zeng, Lei Zhou, Lingheng Meng, Xiang Li, Shaohua Yu
2020	J	`jnl`	A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2020	J	`jnl`	Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
2019	J	`jnl`	A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm. IEICE Electron. Express Huasen Liu, DanYu Wu, Lei Zhou, Jian Luan, Xuan Guo, Dong Wang, Jin Wu, Xinyu Liu
2019	J	`jnl`	A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. IEICE Electron. Express Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu
2019	C	`conf`	A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer. ISCAS DanYu Wu, Lei Zhou, Huasen Liu, Yinkun Huang, Jian Luan, Xuan Guo, Jin Wu, Xinyu Liu
2019	—	`conf`	A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
2019	J	`jnl`	An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz. IEEE Trans. Circuits Syst. II Express Briefs Dong Wang, Lei Zhou, DanYu Wu, Chonghe Ma, Jinxin Xue, Xuan Guo, Jian Luan, Huasen Liu, Jin Wu, Xinyu Liu
2019	—	`conf`	Demonstration of Bidirectional Real-Time 100 Gb/s (4×25 Gb/s) Coherent UDWDM-PON with Power Budget of 44 dB. OFC Ming Luo, DanYu Wu, Weizhong Li, Tao Zeng, Lei Zhou, Lingheng Meng, Zhixue He, Cai Li, Xiang Li
2017	J	`jnl`	A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS. IEICE Electron. Express Xiaoge Zhu, Lei Zhou, DanYu Wu, Jin Wu, Xinyu Liu
2017	J	`jnl`	A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration. IEICE Electron. Express Xiaoge Zhu, DanYu Wu, Lei Zhou, Chonghe Ma, Dandan Wang, Jian Luan, Yinkun Huang, Jin Wu, Xinyu Liu
2017	J	`jnl`	A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology. Sci. China Inf. Sci. Xiaoge Zhu, DanYu Wu, Lei Zhou, Yinkun Huang, Jin Wu, Xinyu Liu
2016	—	`conf`	A 30Gsps 6bit DAC in SiGe BiCMOS technology. ICECS Lei Zhou, Weizhong Li, DanYu Wu, Fan Jiang, Daojun Xue, Jin Wu, Xinyu Liu
2014	J	`jnl`	A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC. Sci. China Inf. Sci. Fan Jiang, DanYu Wu, Lei Zhou, Jin Wu, Zhi Jin, Xinyu Liu