Lei He - RankMe

333 papers A* 42A 61B 10C 4Misc 3Journal 133Unranked 80

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU. ASPLOS (2) Shaoqiang Lu, Yangbo Wei, Junhong Qian, Dongge Qin, Shiji Gao, Yizhi Ding, Qifan Wang, Chen Wu, Xiao Shi, Lei He
2026	A*	`conf`	Mixture-of-Trees: Learning to Select and Weigh Reasoning Paths for Efficient LLM Inference. AAAI Yangbo Wei, Zhen Huang, Shaoqiang Lu, Junhong Qian, Dongge Qin, Ting-Jung Lin, Wei W. Xing, Chen Wu, Lei He
2026	—	`conf`	Multi-Level Interconnect Planning for Signal-Power-Thermal Integrity in 2.5D/3D Integration. ISPD Siyuan Miao, Lingkang Zhu, Xiangqiao Meng, Wenkai Yang, Chengyu Zhu, Chen Wu, Lei He
2026	J	`jnl`	SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation. CoRR Zicheng He, Anhao Zhao, Xiaoyu Shen, Chen Wu, Lei He
2026	—	`conf`	VFlow: Discovering Optimal Agentic Workflows for Verilog Generation. ASP-DAC Yangbo Wei, Zhen Huang, Lei He, Li Huang, Ting-Jung Lin, Wei W. Xing
2026	—	`conf`	dLLM-OPU: An FPGA Overlay Processor for Accelerated Diffusion Large Language Models. ASP-DAC Yangbo Wei, Shaoqiang Lu, Junhong Qian, Lei He, Dongge Qin, Xiao Shi, Chen Wu, Linfeng Zhang
2025	J	`jnl`	AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits. CoRR Yichen Shi, Ze Zhang, Hongyang Wang, Zhuofu Tao, Zhongyi Li, Bingyu Chen, Yaxin Wang, Zhiping Yu, Ting-Jung Lin, Lei He
2025	J	`jnl`	AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection. CoRR Yichen Shi, Zhuofu Tao, Yuhao Gao, Li Huang, Hongyang Wang, Zhiping Yu, Ting-Jung Lin, Lei He
2025	J	`jnl`	AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-design Using Knowledge Graph RAG. ACM Trans. Design Autom. Electr. Syst. Yichen Shi, Zhuofu Tao, Yuhao Gao, Tianjia Zhou, Cheng Chang, Yaxin Wang, Bingyu Chen, Genhao Zhang, Alvin Liu, Zhiping Yu, Ting-Jung Lin, Lei He
2025	—	`conf`	Abuttable Analog Cell Library and Automatic AMS Layout. ISPD Tianjia Zhou, Cheng Chang, Li Huang, Jingyun Gu, Zexin Ji, Xiangyang Liu, Hailang Liang, Zhanfei Chen, Ting-Jung Lin, Song Wang, Na Bai, Zhengping Li, Lei He
2025	J	`jnl`	Automated SAR ADC Sizing Using Analytical Equations. CoRR Zhongyi Li, Zhuofu Tao, Yanze Zhou, Yichen Shi, Zhiping Yu, Ting-Jung Lin, Lei He
2025	Misc	`conf`	C2OPU: Hybrid Compute-in-Memory and Coarse-Grained Reconfigurable Architecture for Overlay Processing of Transformers. FCCM Siyuan Miao, Lingkang Zhu, Chen Wu, Shaoqiang Lu, Jinming Lyu, Lei He
2025	J	`jnl`	Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning. CoRR Tao Bai, Junzhuo Zhou, Zeyuan Deng, Ting-Jung Lin, Wei W. Xing, Peng Cao, Lei He
2025	—	`conf`	LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active Learning. ISPD Junzhuo Zhou, Haoxuan Xia, Wei W. Xing, Ting-Jung Lin, Li Huang, Lei He
2025	J	`jnl`	MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models. ACM Trans. Reconfigurable Technol. Syst. Shaoqiang Lu, Tiandong Zhao, Ting-Jung Lin, Rumin Zhang, Chen Wu, Lei He
2025	—	`conf`	METAL: A Memory-Efficient Transformer Architecture for Long-Context Inference on FPGA. ASAP Zicheng He, Shaoqiang Lu, Tiandong Zhao, Jinlong Yan, Chen Wu, Lei He
2025	A*	`conf`	MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models. DAC Shaoqiang Lu, Xuliang Yu, Tiandong Zhao, Siyuan Miao, Xinsong Sheng, Chen Wu, Liang Zhao, Ting-Jung Lin, Lei He
2025	A	`conf`	MoE-OPU: An FPGA Overlay Processor Leveraging Expert Parallelism for MoE-based Large Language Models. ICCAD Shaoqiang Lu, Yangbo Wei, Junhong Qian, Chen Wu, Xiao Shi, Lei He
2025	J	`jnl`	ModelGen: Automating Semiconductor Parameter Extraction with Large Language Model Agents. ACM Trans. Design Autom. Electr. Syst. Yangbo Wei, Li Huang, Qi Feng, Zhanfei Chen, Jinlong Yan, Ting-Jung Lin, Zhen Huang, Kun Ren, Wei W. Xing, Lei He
2025	A*	`conf`	NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation. DAC Pengju Chen, Dan Niu, Dekang Zhang, Wenhao Wang, Depeng Xie, Zhou Jin, Wei W. Xing, Lei He
2025	J	`jnl`	Productively Generating a High-Performance Linear Algebra Library on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Xiaochen Hao, Mingzhe Zhang, Ce Sun, Zhuofu Tao, Hongbo Rong, Yu Zhang, Lei He, Eric Petit, Wenguang Chen, Yun Liang
2025	J	`jnl`	SHIELD: an evaluation benchmark for face spoofing and forgery detection with multimodal large language models. Vis. Intell. Yichen Shi, Yuhao Gao, Yingxin Lai, Hongyang Wang, Jun Feng, Lei He, Jun Wan, Changsheng Chen, Zitong Yu, Xiaochun Cao
2025	A*	`conf`	Self-Attention to Operator Learning-based 3D-IC Thermal Simulation. DAC Zhen Huang, Hong Wang, Wenkai Yang, Muxi Tang, Depeng Xie, Ting-Jung Lin, Yu Zhang, Wei W. Xing, Lei He
2025	J	`jnl`	Self-Attention to Operator Learning-based 3D-IC Thermal Simulation. CoRR Zhen Huang, Hong Wang, Wenkai Yang, Muxi Tang, Depeng Xie, Ting-Jung Lin, Yu Zhang, Wei W. Xing, Lei He
2025	A	`conf`	SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning. ICCAD Junzhuo Zhou, Ziwen Wang, Haoxuan Xia, Yuxin Yan, Chengyu Zhu, Ting-Jung Lin, Wei W. Xing, Lei He
2025	J	`jnl`	SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning. CoRR Junzhuo Zhou, Ziwen Wang, Haoxuan Xia, Yuxin Yan, Chengyu Zhu, Ting-Jung Lin, Wei W. Xing, Lei He
2025	—	`conf`	Symbol and Footprint Database for Electronic Components by Agentic Recognition and Generation. PRCV (7) Yichen Shi, Yuzhi Liu, Zhuofu Tao, Li Huang, Yuhao Gao, Ting-Jung Lin, Lei He
2025	J	`jnl`	VFlow: Discovering Optimal Agentic Workflows for Verilog Generation. CoRR Yangbo Wei, Zhen Huang, Huang Li, Wei W. Xing, Ting-Jung Lin, Lei He
2024	A	`conf`	AESHA: Accelerating Eigen-decomposition-based Sparse Transformer with Hybrid RRAM-SRAM Architecture. ICCAD Xuliang Yu, Tianwei Ni, Xinsong Sheng, Yun Pan, Lei He, Liang Zhao
2024	J	`jnl`	AMSNet: Netlist Dataset for AMS Circuits. CoRR Zhuofu Tao, Yichen Shi, Yiru Huo, Rui Ye, Zonghang Li, Li Huang, Chen Wu, Na Bai, Zhiping Yu, Ting-Jung Lin, Lei He
2024	J	`jnl`	AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG. CoRR Yichen Shi, Zhuofu Tao, Yuhao Gao, Tianjia Zhou, Cheng Chang, Yaxing Wang, Bingyu Chen, Genhao Zhang, Alvin Liu, Zhiping Yu, Ting-Jung Lin, Lei He
2024	A	`conf`	Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis. ICCAD Yanfang Liu, Lei He, Wei W. Xing
2024	J	`jnl`	Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis. CoRR Yanfang Liu, Lei He, Wei W. Xing
2024	A	`conf`	ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity. ICCAD Tiandong Zhao, Shaoqiang Lu, Chen Wu, Lei He
2024	A*	`conf`	Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield Evaluation. DAC Wei W. Xing, Yanfang Liu, Weijian Fan, Lei He
2024	A*	`conf`	LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning. DAC Junzhuo Zhou, Li Huang, Haoxuan Xia, Yihui Cai, Leilei Jin, Xiao Shi, Wei W. Xing, Ting-Jung Lin, Lei He
2024	J	`jnl`	SHIELD : An Evaluation Benchmark for Face Spoofing and Forgery Detection with Multimodal Large Language Models. CoRR Yichen Shi, Yuhao Gao, Yingxin Lai, Hongyang Wang, Jun Feng, Lei He, Jun Wan, Changsheng Chen, Zitong Yu, Xiaochun Cao
2023	J	`jnl`	LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator. ACM Trans. Reconfigurable Technol. Syst. Zhuofu Tao, Chen Wu, Yuan Liang, Kun Wang, Lei He
2023	Misc	`conf`	Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs. FCCM Xiaochen Hao, Mingzhe Zhang, Ce Sun, Zhuofu Tao, Hongbo Rong, Yu Zhang, Lei He, Eric Petit, Wenguang Chen, Yun Liang
2023	—	`conf`	MDT-Net: Multi-Domain Transfer by Perceptual Supervision for Unpaired Images in OCT Scan. ISBI Weinan Song, Gaurav Fotedar, Nima Tajbakhsh, Ziheng Zhou, Lei He, Xiaowei Ding
2023	J	`jnl`	Oral-NeXF: 3D Oral Reconstruction with Neural X-ray Field from Panoramic Imaging. CoRR Weinan Song, Haoxin Zheng, Jiawei Yang, Chengwen Liang, Lei He
2023	J	`jnl`	Progressive Energy-Based Cooperative Learning for Multi-Domain Image-to-Image Translation. CoRR Weinan Song, Yaxuan Zhu, Lei He, Yingnian Wu, Jianwen Xie
2023	B	`conf`	Token Packing for Transformers with Variable-Length Inputs. FPL Tiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang, Lei He
2022	J	`jnl`	A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation. ACM Trans. Design Autom. Electr. Syst. Xiao Shi, Hao Yan, Qiancun Huang, Chengzhen Xuan, Lei He, Longxing Shi
2022	J	`jnl`	An IoT-based intelligent irrigation system with data fusion and a self-powered wide-area network. J. Ind. Inf. Integr. Li Gong, Jinlong Yan, Yiqiao Chen, Jinjing An, Lei He, Lirong Zheng, Zhuo Zou
2022	J	`jnl`	BCmaster: A Compatible Framework for Comprehensively Analyzing and Monitoring Blockchain Systems in IoT. IEEE Internet Things J. Yinqiu Liu, Kai Qian, Kun Wang, Lei He
2022	—	`conf`	ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images. ECCV (21) Jiawei Yang, Hanbo Chen, Yuan Liang, Junzhou Huang, Lei He, Jianhua Yao
2022	J	`jnl`	ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images. CoRR Jiawei Yang, Hanbo Chen, Yuan Liang, Junzhou Huang, Lei He, Jianhua Yao
2022	J	`jnl`	Effective Scaling of Blockchain Beyond Consensus Innovations and Moore's Law: Challenges and Opportunities. IEEE Syst. J. Yinqiu Liu, Kai Qian, Kun Wang, Lei He
2022	J	`jnl`	Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration. ACM Trans. Reconfigurable Technol. Syst. Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He
2022	—	`conf`	ReMix: A General and Efficient Framework for Multiple Instance Learning Based Whole Slide Image Classification. MICCAI (2) Jiawei Yang, Hanbo Chen, Yu Zhao, Fan Yang, Yao Zhang, Lei He, Jianhua Yao
2022	J	`jnl`	ReMix: A General and Efficient Framework for Multiple Instance Learning based Whole Slide Image Classification. CoRR Jiawei Yang, Hanbo Chen, Yu Zhao, Fan Yang, Yao Zhang, Lei He, Jianhua Yao
2022	B	`conf`	SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training. FPL Chen Wu, Zhuofu Tao, Kun Wang, Lei He
2022	A*	`conf`	TreeMoCo: Contrastive Neuron Morphology Representation Learning. NeurIPS Hanbo Chen, Jiawei Yang, Daniel Maxim Iascone, Lijuan Liu, Lei He, Hanchuan Peng, Jianhua Yao
2021	J	`jnl`	Atlas-aware ConvNetfor Accurate yet Robust Anatomical Segmentation. CoRR Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He
2021	J	`jnl`	Channel-Correlation-Enabled Transmission Optimization for MISO Wiretap Channels. IEEE Trans. Wirel. Commun. Shuai Han, Sai Xu, Weixiao Meng, Lei He
2021	J	`jnl`	Editorial for FGCS special issue: Computation Intelligence for Energy Internet. Future Gener. Comput. Syst. Yan Zhang, Kun Wang, Lei He
2021	A*	`conf`	Exploring Forensic Dental Identification with Deep Learning. NeurIPS Yuan Liang, Weikun Han, Liang Qiu, Chen Wu, Yiting Shao, Kun Wang, Lei He
2021	—	`conf`	Exploring Instance-Level Uncertainty for Medical Detection. ISBI Jiawei Yang, Yuan Liang, Yao Zhang, Weinan Song, Kun Wang, Lei He
2021	Misc	`conf`	Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs. FCCM Tiandong Zhao, Yunxuan Yu, Kun Wang, Lei He
2021	J	`jnl`	Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs. CoRR Tiandong Zhao, Yunxuan Yu, Kun Wang, Lei He
2021	J	`jnl`	LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator. CoRR Zhuofu Tao, Chen Wu, Yuan Liang, Lei He
2021	B	`conf`	MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks. FPL Chen Wu, Jinming Zhuang, Kun Wang, Lei He
2021	A	`conf`	NPE: An FPGA-based Overlay Processor for Natural Language Processing. FPGA Hamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He
2021	J	`jnl`	NPE: An FPGA-based Overlay Processor for Natural Language Processing. CoRR Hamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He
2021	A*	`conf`	Oral-3D: Reconstructing the 3D Structure of Oral Cavity from Panoramic X-ray. AAAI Weinan Song, Yuan Liang, Jiawei Yang, Kun Wang, Lei He
2021	A	`conf`	OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray. IUI Yuan Liang, Liang Qiu, Tiancheng Lu, Zhujun Fang, Dezhan Tu, Jiawei Yang, Yiting Shao, Kun Wang, Xiang 'Anthony' Chen, Lei He
2021	J	`jnl`	OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray. CoRR Yuan Liang, Liang Qiu, Tiancheng Lu, Zhujun Fang, Dezhan Tu, Jiawei Yang, Tiandong Zhao, Yiting Shao, Kun Wang, Xiang 'Anthony' Chen, Lei He
2021	—	`conf`	T-Net: Learning Feature Representation With Task-Specific Supervision For Biomedical Image Analysis. ISBI Weinan Song, Yuan Liang, Jiawei Yang, Kun Wang, Lei He
2021	—	`conf`	TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation. MICCAI (1) Jiawei Yang, Yao Zhang, Yuan Liang, Yang Zhang, Lei He, Zhiqiang He
2021	J	`jnl`	TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation. CoRR Jiawei Yang, Yao Zhang, Yuan Liang, Yang Zhang, Lei He, Zhiqiang He
2021	J	`jnl`	X2Teeth: 3D Teeth Reconstruction from a Single Panoramic Radiograph. CoRR Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He
2020	A	`conf`	A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis. ICCAD Xiao Shi, Hao Yan, Chuwen Li, Jianli Chen, Longxing Shi, Lei He
2020	J	`jnl`	Accurate Anchor Free Tracking. CoRR Shengyun Peng, Yunxuan Yu, Kun Wang, Lei He
2020	J	`jnl`	An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiao Shi, Hao Yan, Jinxin Wang, Jiajia Zhang, Longxing Shi, Lei He
2020	C	`conf`	Atlas-aware ConvNet for Accurate yet Robust Anatomical Segmentation. ACML Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He
2020	J	`jnl`	Correlation-Based Cooperative Jamming to Enhance Secrecy With Receiver-Side Correlation. IEEE Trans. Veh. Technol. Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He
2020	J	`jnl`	Correlation-Based Secure Transmission for Correlated MISO Wiretap Channels. IEEE Wirel. Commun. Lett. Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He
2020	J	`jnl`	Effective scaling of blockchain beyond consensus innovations and Moore's law. CoRR Yinqiu Liu, Kai Qian, Jinlong Yu, Kun Wang, Lei He
2020	J	`jnl`	Exploring Instance-Level Uncertainty for Medical Detection. CoRR Jiawei Yang, Yuan Liang, Yao Zhang, Weinan Song, Kun Wang, Lei He
2020	A	`conf`	Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks. FPGA Yunxuan Yu, Tiandong Zhao, Kun Wang, Lei He
2020	A	`conf`	Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration. FPGA Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He
2020	J	`jnl`	OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Yunxuan Yu, Chen Wu, Tiandong Zhao, Kun Wang, Lei He
2020	J	`jnl`	Oral-3D: Reconstructing the 3D Bone Structure of Oral Cavity from 2D Panoramic X-ray. CoRR Weinan Song, Yuan Liang, Kun Wang, Lei He
2020	A*	`conf`	OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera. CHI Yuan Liang, Hsuan-Wei Fan, Zhujun Fang, Leiying Miao, Wen Li, Xuan Zhang, Weibin Sun, Kun Wang, Lei He, Xiang Anthony Chen
2020	J	`jnl`	OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera. CoRR Yuan Liang, Hsuan-Wei Fan, Zhujun Fang, Leiying Miao, Wen Li, Xuan Zhang, Weibin Sun, Kun Wang, Lei He, Xiang Anthony Chen
2020	J	`jnl`	QoS-Based Robust Cooperative-Jamming-Aided Beamforming for Correlated Wiretap Channels. IEEE Signal Process. Lett. Sai Xu, Shuai Han, Weixiao Meng, Lei He
2020	J	`jnl`	Robust Beamforming Design for Correlated MISO Wiretap Channels Under Channel Uncertainty. IEEE Wirel. Commun. Lett. Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He
2020	J	`jnl`	T-Net: A Template-Supervised Network for Task-specific Feature Extraction in Biomedical Image Analysis. CoRR Weinan Song, Yuan Liang, Kun Wang, Lei He
2020	J	`jnl`	Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks. IEEE Trans. Very Large Scale Integr. Syst. Yunxuan Yu, Tiandong Zhao, Mingyu Wang, Kun Wang, Lei He
2020	—	`conf`	X2Teeth: 3D Teeth Reconstruction from a Single Panoramic Radiograph. MICCAI (2) Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He
2019	J	`jnl`	AN-Aided Secure Beamforming Design for Correlated MISO Wiretap Channels. IEEE Commun. Lett. Sai Xu, Shuai Han, Yanan Du, Weixiao Meng, Lei He, Chengwen Zhang
2019	—	`conf`	Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis. ISPD Xiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi, Lei He
2019	—	`conf`	Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling. ASICON Xiao Shi, Jinlong Yan, Hao Yan, Jiajia Zhang, Jinxin Wang, Longxing Shi, Lei He
2019	A	`conf`	Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang
2019	J	`jnl`	Channel-Correlation-Enabled Transmit Optimization for MISO Wiretap Channels. CoRR Shuai Han, Sai Xu, Weixiao Meng, Lei He
2019	—	`conf`	CompareNet: Anatomical Segmentation Network with Deep Non-local Label Fusion. MICCAI (3) Yuan Liang, Weinan Song, J. P. Dym, Kun Wang, Lei He
2019	J	`jnl`	CompareNet: Anatomical Segmentation Network with Deep Non-local Label Fusion. CoRR Yuan Liang, Weinan Song, J. P. Dym, Kun Wang, Lei He
2019	A	`conf`	Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method. ICCAD Xiao Shi, Hao Yan, Jiajia Zhang, Qiancun Huang, Longxing Shi, Lei He
2019	A*	`conf`	Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation. DAC Xiao Shi, Hao Yan, Qiancun Huang, Jiajia Zhang, Longxing Shi, Lei He
2019	J	`jnl`	Multiple-Jammer-Aided Secure Transmission With Receiver-Side Correlation. IEEE Trans. Wirel. Commun. Sai Xu, Shuai Han, Wei-Xiao Meng, Yanan Du, Lei He
2019	A	`conf`	Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang
2018	A*	`conf`	A fast and robust failure analysis of memory circuits using adaptive importance sampling method. DAC Xiao Shi, Fengyuan Liu, Jun Yang, Lei He
2018	J	`jnl`	Fast iteratively reweighted least squares algorithms for analysis-based sparse reconstruction. Medical Image Anal. Chen Chen, Lei He, Hongsheng Li, Junzhou Huang
2018	J	`jnl`	IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications - Part II. IEEE Access Kun Wang, Yan Zhang, Song Guo, Mianxiong Dong, Rose Qingyang Hu, Lei He
2018	J	`jnl`	IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications. IEEE Access Kun Wang, Yan Zhang, Song Guo, Mianxiong Dong, Rose Qingyang Hu, Lei He
2018	J	`jnl`	Probabilistic Model Checking and Scheduling Implementation of an Energy Router System in Energy Internet for Green Cities. IEEE Trans. Ind. Informatics Min Gao, Kun Wang, Lei He
2018	J	`jnl`	Recurrent Neural Networks with Pre-trained Language Model Embedding for Slot Filling Task. CoRR Liang Qiu, Yuanyi Ding, Lei He
2018	A	`conf`	Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only). FPGA Juexiao Su, Lei He
2017	A*	`conf`	Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length. DAC Juexiao Su, Lei He
2017	J	`jnl`	Grain Price Forecasting Using a Hybrid Stochastic Method. Asia Pac. J. Oper. Res. Yu Zhao, Xi Zhang, Zhongshun Shi, Lei He
2017	J	`jnl`	Layout driven FPGA packing algorithm for performance optimization. IEICE Electron. Express Linfeng Mo, Chang Wu, Lei He, Gengsheng Chen
2017	J	`jnl`	Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems. IEEE Access Jinlong Yan, Qi Zeng, Yuan Liang, Lei He, Zhengping Li
2017	B	`conf`	Probabilistic Model Checking for Green Energy Router System in Energy Internet. GLOBECOM Min Gao, Kun Wang, Lei He
2016	A*	`conf`	A quantum annealing approach for boolean satisfiability problem. DAC Juexiao Su, Tianheng Tu, Lei He
2016	A	`conf`	FPGA Power Estimation Using Automatic Feature Selection (Abstract Only). FPGA Yunxuan Yu, Lei He
2016	—	`conf`	Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage. ISPD Wei Wu, Srinivas Bodapati, Lei He
2016	C	`conf`	LLSPLAT: Improving Concolic Testing by Bounded Model Checking. SCAM Min Gao, Lei He, Rupak Majumdar, Zilong Wang
2016	J	`jnl`	Sampling and Reconstruction in Arbitrary Measurement and Approximation Spaces Associated With Linear Canonical Transform. IEEE Trans. Signal Process. Jun Shi, Xiaoping Liu, Lei He, Mo Han, Qingzhong Li, Naitong Zhang
2016	C	`conf`	Wave digital filter based analog circuit emulation on FPGA. ISCAS Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
2015	J	`jnl`	A Game Theory-Based Energy Management System Using Price Elasticity for Smart Grids. IEEE Trans. Ind. Informatics Kun Wang, Zhiyou Ouyang, Rahul Krishnan, Lei Shu, Lei He
2015	—	`conf`	A Social Awareness based Feedback Mechanism for delivery reliability in Delay Tolerant Networks. ICC Kun Wang, Guo Huang, Lei Shu, Chunsheng Zhu, Lei He
2015	—	`conf`	An improved spray and wait algorithm based on RVNS in Delay Tolerant Mobile Sensor Networks. ICC Kun Wang, Yun Shao, Lei Shu, Yanfei Sun, Lei He
2015	—	`conf`	Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He
2015	A	`conf`	Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
2014	—	`conf`	A fast and provably bounded failure analysis of memory circuits in high dimensions. ASP-DAC Wei Wu, Fang Gong, Gengsheng Chen, Lei He
2014	B	`conf`	Accelerating the iterative linear solver for reservoir simulation on multicore architectures. ICPADS Wei Wu, Xiang Li, Lei He, Dongxiao Zhang
2014	J	`jnl`	Fast Iteratively Reweighted Least Squares Algorithms for Analysis-Based Sparsity Reconstruction. CoRR Chen Chen, Junzhou Huang, Lei He, Hongsheng Li
2014	J	`jnl`	IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Zhe Feng, Naifeng Jing, Lei He
2014	A*	`conf`	Preconditioning for Accelerated Iteratively Reweighted Least Squares in Structured Sparsity Reconstruction. CVPR Chen Chen, Junzhou Huang, Lei He, Hongsheng Li
2014	A*	`conf`	REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. DAC Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He
2014	J	`jnl`	Statistical timing and power analysis of VLSI considering non-linear dependence. Integr. Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He
2014	J	`jnl`	Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges. IEEE Des. Test Fang Gong, Hao Yu, Yiyu Shi, Lei He
2013	J	`jnl`	Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. IEEE Des. Test Wei Wu, Fang Gong, Rahul Krishnan, Lei He, Hao Yu
2013	J	`jnl`	Fast Filter-Based Boolean Matchers. IEEE Embed. Syst. Lett. Chaofan Yu, Lingli Wang, Chun Zhang, Yu Hu, Lei He
2013	—	`conf`	Inconspicuous Personal Computer Protection with Touch-Mouse. HCI (27) Ming-Chun Huang, Wenyao Xu, Jason J. Liu, Yi Su, Lei He, Majid Sarrafzadeh
2013	J	`jnl`	Modeling and Application of Multi-Port TSV Networks in 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Yao, Siming Pan, Brice Achkir, Jun Fan, Lei He
2013	J	`jnl`	Object Matching Using a Locally Affine Invariant and Linear Programming Techniques. IEEE Trans. Pattern Anal. Mach. Intell. Hongsheng Li, Xiaolei Huang, Lei He
2013	J	`jnl`	SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integr. Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He
2013	J	`jnl`	Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fang Gong, Sina Basir-Kazeruni, Lei He, Hao Yu
2013	—	`conf`	Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy. ISQED Rahul Krishnan, Wei Wu, Fang Gong, Lei He
2012	J	`jnl`	A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He
2012	J	`jnl`	A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments. IEEE Trans. Very Large Scale Integr. Syst. Fang Gong, Hao Yu, Lingli Wang, Lei He
2012	—	`conf`	A fast estimation of SRAM failure rate using probability collectives. ISPD Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He
2012	J	`jnl`	Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. Lerong Cheng, Fang Gong, Wenyao Xu, Jinjun Xiong, Lei He, Majid Sarrafzadeh
2012	—	`conf`	Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. FPT Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He
2012	J	`jnl`	NeuroGlasses: A Neural Sensing Healthcare System for 3-D Vision Technology. IEEE Trans. Inf. Technol. Biomed. Fang Gong, Wenyao Xu, Jueh-Yu Lee, Lei He, Majid Sarrafzadeh
2012	J	`jnl`	SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
2012	—	`conf`	Smart insole: a wearable system for gait analysis. PETRA Wenyao Xu, Ming-Chun Huang, Navid Amini, Jason J. Liu, Lei He, Majid Sarrafzadeh
2012	J	`jnl`	Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He
2012	J	`jnl`	Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. IEEE Trans. Very Large Scale Integr. Syst. Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
2011	B	`conf`	Acceleration of Multi-agent Simulation on FPGAs. FPL Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He
2011	A*	`conf`	Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials. DAC Fang Gong, Hao Yu, Lei He
2011	A	`conf`	Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He
2011	B	`conf`	IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL Zhe Feng, Naifeng Jing, Gengsheng Chen, Yu Hu, Lei He
2011	J	`jnl`	In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Trans. Circuits Syst. I Regul. Pap. Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh
2011	A	`conf`	Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
2011	J	`jnl`	Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He
2011	B	`conf`	Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
2011	J	`jnl`	Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator. IEEE Trans. Very Large Scale Integr. Syst. Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He
2011	—	`conf`	Stochastic analog circuit behavior modeling by point estimation method. ISPD Fang Gong, Hao Yu, Lei He
2011	J	`jnl`	System-in-Package: Electrical and Layout Perspectives. Found. Trends Electron. Des. Autom. Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao
2010	A*	`conf`	A universal state-of-charge algorithm for batteries. DAC Bingjun Xiao, Yiyu Shi, Lei He
2010	J	`jnl`	Accelerating Boolean Matching Using Bloom Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010	A	`conf`	Building a faster boolean matcher using bloom filter. FPGA Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010	J	`jnl`	EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization. IEEE Trans. Very Large Scale Integr. Syst. Yiyu Shi, Lei He
2010	J	`jnl`	Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
2010	A	`conf`	Engineering a scalable Boolean matching based on EDA SaaS 2.0. ICCAD Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
2010	J	`jnl`	Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. IEEE Trans. Very Large Scale Integr. Syst. Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan
2010	—	`conf`	Fault-tolerant resynthesis with dual-output LUTs. ASP-DAC Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
2010	A	`conf`	In-place decomposition for robustness in FPGA. ICCAD Ju-Yueh Lee, Zhe Feng, Lei He
2010	A	`conf`	Modeling and design for beyond-the-die power integrity. ICCAD Yiyu Shi, Lei He
2010	A*	`conf`	Object matching with a locally affine-invariant constraint. CVPR Hongsheng Li, Edward Kim, Xiaolei Huang, Lei He
2010	—	`conf`	On confidence in characterization and application of variation models. ASP-DAC Lerong Cheng, Puneet Gupta, Lei He
2010	J	`jnl`	Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar
2010	A*	`conf`	QuickYield: an efficient global-search based parametric yield estimation with performance constraints. DAC Fang Gong, Hao Yu, Yiyu Shi, DaeSoo Kim, Junyan Ren, Lei He
2010	A	`conf`	RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. DATE Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2010	A*	`conf`	Rewiring for robustness. DAC Manu Jose, Yu Hu, Rupak Majumdar, Lei He
2010	J	`jnl`	Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng
2009	—	`conf`	Accounting for non-linear dependence using function driven component analysis. ASP-DAC Lerong Cheng, Puneet Gupta, Lei He
2009	J	`jnl`	Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Trans. Design Autom. Electr. Syst. Hao Yu, Joanna Ho, Lei He
2009	J	`jnl`	Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Hu, Satyaki Das, Steven Trimberger, Lei He
2009	—	`conf`	Diffusion-driven congestion reduction for substrate topological routing. ISPD Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
2009	J	`jnl`	Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lerong Cheng, Puneet Gupta, Lei He
2009	A	`conf`	IPR: In-Place Reconfiguration for FPGA fault tolerance. ICCAD Zhe Feng, Yu Hu, Lei He, Rupak Majumdar
2009	—	`conf`	Incremental and on-demand random walk for iterative power distribution network analysis. ASP-DAC Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He
2009	A	`conf`	Joint design-time and post-silicon optimization for digitally tuned analog circuits. ICCAD Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
2009	J	`jnl`	Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lerong Cheng, Jinjun Xiong, Lei He
2009	A*	`conf`	Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He
2009	A*	`conf`	PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. DAC Fang Gong, Hao Yu, Lei He
2009	J	`jnl`	Robust On-Chip Signaling by Staggered and Twisted Bundle. IEEE Des. Test Comput. Hao Yu, Lei He, Mau-Chung Frank Chang
2009	—	`conf`	Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2009	—	`conf`	Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. ASP-DAC Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He
2009	J	`jnl`	Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
2009	—	`conf`	Worst case timing jitter and amplitude noise in differential signaling. ISQED Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu
2008	J	`jnl`	Dual-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang
2008	J	`jnl`	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He
2008	J	`jnl`	Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2008	A*	`conf`	FPGA area reduction by multi-output function based sequential resynthesis. DAC Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2008	J	`jnl`	Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong
2008	—	`conf`	Non-Gaussian statistical timing analysis using second-order polynomial fitting. ASP-DAC Lerong Cheng, Jinjun Xiong, Lei He
2008	A*	`conf`	Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. DAC Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar
2008	J	`jnl`	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. Yu Hu, Yan Lin, Lei He, Tim Tuan
2008	A	`conf`	Robust FPGA resynthesis based on fault-tolerant Boolean matching. ICCAD Yu Hu, Zhe Feng, Lei He, Rupak Majumdar
2008	—	`conf`	Scalable Symbolic Model Order Reduction. BMAS Yiyu Shi, Lei He, Chuanjin Richard Shi
2008	J	`jnl`	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Yan Lin, Lei He, Mike Hutton
2008	J	`jnl`	Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. Very Large Scale Integr. Syst. Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2008	A*	`conf`	Topological routing to maximize routability for package substrate. DAC Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
2008	A	`conf`	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA Lerong Cheng, Yan Lin, Lei He
2007	J	`jnl`	Circuit-simulated obstacle-aware Steiner routing. ACM Trans. Design Autom. Electr. Syst. Yiyu Shi, Paul Mesa, Hao Yu, Lei He
2007	A	`conf`	Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ICCAD Yu Hu, Satyaki Das, Steven Trimberger, Lei He
2007	J	`jnl`	Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He
2007	A	`conf`	Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD Yan Lin, Lei He
2007	—	`conf`	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong
2007	J	`jnl`	Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Chen, Lei He
2007	A	`conf`	Efficient decoupling capacitance budgeting considering operation and process variations. ICCAD Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He
2007	—	`conf`	Empire: an efficient and compact multiple-parameterized model order reduction method. ISPD Yiyu Shi, Lei He
2007	A	`conf`	Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD Yu Hu, Victor Shih, Rupak Majumdar, Lei He
2007	—	`conf`	Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP Yu Hu, King Ho Tam, Tong Jing, Lei He
2007	J	`jnl`	Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Li, Yan Lin, Lei He
2007	J	`jnl`	Full-chip multilevel routing for power and signal integrity. Integr. Jinjun Xiong, Lei He
2007	A	`conf`	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE Yan Lin, Lei He
2007	J	`jnl`	Microarchitecture Configurations and Floorplanning Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He
2007	—	`conf`	Minimal skew clock embedding considering time variant temperature gradient. ISPD Hao Yu, Yu Hu, Chunchen Liu, Lei He
2007	A*	`conf`	Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. DAC Lerong Cheng, Jinjun Xiong, Lei He
2007	A*	`conf`	Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. DAC Hao Yu, Chunta Chu, Lei He
2007	J	`jnl`	Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinjun Xiong, Lei He
2007	J	`jnl`	Robust Extraction of Spatial Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinjun Xiong, Vladimir Zolotov, Lei He
2007	J	`jnl`	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2007	J	`jnl`	Statistical placement for FPGAs considering. IET Comput. Digit. Tech. Yan Lin, Mike Hutton, Lei He
2007	A	`conf`	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA Yan Lin, Lei He
2007	A	`conf`	Temperature aware microprocessor floorplanning considering application dependent power load. ICCAD Chunta Chu, Xinyi Zhang, Lei He, Tong Jing
2007	J	`jnl`	TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He
2006	A	`conf`	A fast block structure preserving model order reduction for inverse inductance circuits. ICCAD Hao Yu, Yiyu Shi, Lei He, David Smart
2006	A	`conf`	An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED Yan Lin, Yu Hu, Lei He, Vijay Raghunat
2006	—	`conf`	CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong
2006	A*	`conf`	Circuit simulation based obstacle-aware Steiner routing. DAC Yiyu Shi, Paul Mesa, Hao Yu, Lei He
2006	—	`conf`	Constraint driven I/O planning and placement for chip-package co-design. ASP-DAC Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
2006	J	`jnl`	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yan Lin, Lei He
2006	B	`conf`	FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
2006	A*	`conf`	Fast analysis of structured power grid by triangularization based structure preserving model order reduction. DAC Hao Yu, Yiyu Shi, Lei He
2006	—	`conf`	Fast buffer insertion considering process variations. ISPD Jinjun Xiong, Lei He
2006	J	`jnl`	Modeling and synthesis of multiport transmission line for multichannel communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Chen, Lei He
2006	—	`conf`	Noise driven in-package decoupling capacitor optimization for power integrity. ISPD Jun Chen, Lei He
2006	B	`conf`	Placement and Timing for FPGAs Considering Variations. FPL Mike Hutton, Yan Lin, Lei He
2006	A	`conf`	Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik
2006	—	`conf`	Robust extraction of spatial correlation. ISPD Jinjun Xiong, Vladimir Zolotov, Lei He
2006	—	`conf`	SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. ISPD Yiyu Shi, Hao Yu, Lei He
2006	A	`conf`	Simultaneous power and thermal integrity driven via stapling in 3D ICs. ICCAD Hao Yu, Joanna Ho, Lei He
2006	A*	`conf`	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC Yu Hu, Yan Lin, Lei He, Tim Tuan
2006	A	`conf`	Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2006	J	`jnl`	Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He
2005	—	`conf`	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He
2005	J	`jnl`	A provably passive and cost-efficient model for inductive interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Yu, Lei He
2005	—	`conf`	A sparsified vector potential equivalent circuit model for massively coupled interconnects. ISCAS (1) Hao Yu, Lei He
2005	—	`conf`	A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
2005	A	`conf`	An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He
2005	A	`conf`	Buffer Insertion Considering Process Variation. DATE Jinjun Xiong, King Ho Tam, Lei He
2005	A	`conf`	Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton
2005	J	`jnl`	Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. Yan Lin, Fei Li, Lei He
2005	A*	`conf`	Device and architecture co-optimization for FPGA power reduction. DAC Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
2005	J	`jnl`	Extended global routing with RLC crosstalk constraints. IEEE Trans. Very Large Scale Integr. Syst. Jinjun Xiong, Lei He
2005	A	`conf`	FPGA device and architecture evaluation considering process variations. ICCAD Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
2005	A*	`conf`	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC Yan Lin, Lei He
2005	—	`conf`	Micro-architecture Performance Estimation by Formula. SAMOS Lucanus J. Simonson, Lei He
2005	J	`jnl`	Microarchitecture Level Interconnect Modeling Considering Layout Optimization. J. Low Power Electron. Weiping Liao, Lei He
2005	J	`jnl`	Microarchitecture-level leakage reduction with data retention. IEEE Trans. Very Large Scale Integr. Syst. Weiping Liao, Joseph M. Basile, Lei He
2005	—	`conf`	Modeling and Design of Chip-Package Interface. ISQED Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He
2005	J	`jnl`	Piecewise linear model for transmission line with capacitive loading and ramp input. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Chen, Lei He
2005	A	`conf`	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA Yan Lin, Fei Li, Lei He
2005	J	`jnl`	Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
2005	A*	`conf`	Power optimal dual-Vdd buffered tree considering buffer stations and blockages. DAC King Ho Tam, Lei He
2005	A	`conf`	Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ISLPED Yu Ching Chang, King Ho Tam, Lei He
2005	—	`conf`	Probabilistic congestion model considering shielding for crosstalk reduction. ASP-DAC Jinjun Xiong, Lei He
2005	—	`conf`	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC Yan Lin, Fei Li, Lei He
2005	A	`conf`	Scheduling of Soft Real-Time Systems for Context-Aware Applications. DATE Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak
2005	—	`conf`	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2005	—	`conf`	Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. ISQED Hao Yu, Lei He
2005	J	`jnl`	Temperature and supply Voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weiping Liao, Lei He, Kevin M. Lepak
2005	—	`conf`	Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
2005	J	`jnl`	Worst case crosstalk noise for nonswitching victims in high-speed buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jun Chen, Lei He
2004	J	`jnl`	Distributed sleep transistor network for power reduction. IEEE Trans. Very Large Scale Integr. Syst. Changbo Long, Lei He
2004	A*	`conf`	FPGA power reduction using configurable dual-Vdd. DAC Fei Li, Yan Lin, Lei He
2004	A*	`conf`	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. DAC Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He
2004	A	`conf`	Full-Chip Multilevel Routing for Power and Signal Integrity. DATE Jinjun Xiong, Lei He
2004	J	`jnl`	Full-chip routing optimization with RLC crosstalk budgeting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinjun Xiong, Lei He
2004	—	`conf`	High-level area and power-up current estimation considering rich cell library. ASP-DAC Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
2004	—	`conf`	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. ISQED Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He
2004	A	`conf`	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA Fei Li, Yan Lin, Lei He, Jason Cong
2004	A	`conf`	Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA Deming Chen, Jason Cong, Fei Li, Lei He
2004	—	`conf`	Modeling of coplanar waveguide for buffered clock tree. ASP-DAC Jun Chen, Lei He
2004	—	`conf`	On optimal physical synthesis of sleep transistors. ISPD Changbo Long, Jinjun Xiong, Lei He
2004	—	`conf`	Performance and RLC crosstalk driven global routing. ISCAS (5) Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He
2004	—	`conf`	Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
2004	J	`jnl`	Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ACM Trans. Design Autom. Electr. Syst. Kevin M. Lepak, Min Xu, Jun Chen, Lei He
2004	A*	`conf`	System level leakage reduction considering the interdependence of temperature and leakage. DAC Lei He, Weiping Liao, Mircea R. Stan
2004	A	`conf`	Vdd programmability to reduce FPGA interconnect power. ICCAD Fei Li, Yan Lin, Lei He
2003	A	`conf`	Architecture evaluation for power-efficient FPGAs. FPGA Fei Li, Deming Chen, Lei He, Jason Cong
2003	—	`conf`	Coupled Power and Thermal Simulation with Active Cooling. PACS Weiping Liao, Lei He
2003	—	`conf`	Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects. ASP-DAC Jun Chen, Lei He
2003	A*	`conf`	Distributed sleep transistor network for power reduction. DAC Changbo Long, Lei He
2003	A	`conf`	Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion. ICCAD Weiping Liao, Lei He
2003	—	`conf`	High Level Area and Current Estimation. PATMOS Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
2003	A	`conf`	Microarchitecture level power and thermal simulation considering temperature dependent leakage model. ISLPED Weiping Liao, Fei Li, Lei He
2003	A*	`conf`	Vector potential equivalent circuit based on PEEC inversion. DAC Hao Yu, Lei He
2002	—	`conf`	A decoupling method for analysis of coupled RLC interconnects. ACM Great Lakes Symposium on VLSI Jun Chen, Lei He
2002	—	`conf`	Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. Timing Issues in the Specification and Synthesis of Digital Systems Jun Chen, Lei He
2002	—	`conf`	Estimation of Maximum Power-Up Current. ASP-DAC/VLSI Design Fei Li, Lei He, Kewal K. Saluja
2002	A	`conf`	Leakage power modeling and reduction with data retention. ICCAD Weiping Liao, Joseph M. Basile, Lei He
2002	A	`conf`	Post global routing RLC crosstalk budgeting. ICCAD Jinjun Xiong, Jun Chen, James D. Z. Ma, Lei He
2002	A*	`conf`	Towards global routing with RLC crosstalk constraints. DAC James D. Z. Ma, Lei He
2001	—	`conf`	An efficient analytical model of coupled on-chip RLC interconnects. ASP-DAC Liang Yin, Lei He
2001	—	`conf`	An efficient model for frequency-dependent on-chip inductance. ACM Great Lakes Symposium on VLSI Min Xu, Lei He
2001	A	`conf`	Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering. ICCAD James D. Z. Ma, Lei He
2001	—	`conf`	Instruction Prediction for Step Power Reduction. ISQED Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa
2001	J	`jnl`	Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
2001	—	`conf`	Maximum current estimation considering power gating. ISPD Fei Li, Lei He
2001	C	`conf`	Pre-routing Estimation of Shielding for RLC Signal Integrity. ICCD James D. Z. Ma, Arvind Parihar, Lei He
2001	A*	`conf`	Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint. DAC Kevin M. Lepak, Irwan Luwandi, Lei He
2001	—	`conf`	Simultaneous signal and power routing under K model. SLIP James D. Z. Ma, Lei He
2000	A	`conf`	Clocktree RLC Extraction with Efficient Inductance Modeling. DATE Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He
2000	—	`conf`	Ramp Up/Down Functional Unit to Reduce Step Power. PACS Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He
2000	—	`conf`	Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ISPD Lei He, Kevin M. Lepak
1999	—	`conf`	An efficient inductance modeling for on-chip interconnects. CICC Lei He, Norman Chang, Shen Lin, O. Sam Nakagawa
1999	J	`jnl`	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Lei He
1998	—	`conf`	An efficient technique for device and interconnect optimization in deep submicron designs. ISPD Jason Cong, Lei He
1997	A*	`conf`	Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
1997	A	`conf`	Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
1997	A	`conf`	Interconnect design for deep submicron ICs. ICCAD Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
1996	A	`conf`	An efficient approach to simultaneous transistor and interconnect sizing. ICCAD Jason Cong, Lei He
1996	J	`jnl`	Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Lei He
1996	J	`jnl`	Performance optimization of VLSI interconnect layout. Integr. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
1995	A	`conf`	Optimal wiresizing for interconnects with multiple sources. ICCAD Jason Cong, Lei He