Leendert M. Huisman

20 papers A* 2A 8Misc 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2004 A conf
Data Mining Integrated Circuit Fails with Fail Commonalities.
ITC
Leendert M. Huisman, Maroun Kassab, Leah Pastel
2004 J jnl
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Leendert M. Huisman
2003 Misc conf
Analysis and Design of Optimal Combinational Compactors.
VTS
Peter Wohl, Leendert M. Huisman
2001 A conf
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm.
ITC
Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski
1998 A conf
Correlations between path delays and the accuracy of performance prediction.
ITC
Leendert M. Huisman
1998 A conf
Diagnosis and characterization of timing-related defects by time-dependent light emission.
ITC
Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika
1995 J jnl
Yield fluctuations and defect models.
J. Electron. Test.
Leendert M. Huisman
1994 J jnl
Highly Reliable Symmetric Networks.
IEEE Trans. Parallel Distributed Syst.
Leendert M. Huisman, Sandip Kundu
1994 A conf
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability.
ITC
Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman
1992 A conf
A Small Test Generator for Large Designs.
ITC
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
1991 — conf
Symbolic implication in test generation.
EURO-DAC
Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar
1990 A conf
Fault simulation of logic designs on parallel processors with distributed memory.
ITC
Leendert M. Huisman, Raja Daoud
1988 J jnl
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
1988 J jnl
TRIM: testability range by ignoring the memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Larry Carter, Leendert M. Huisman, Tom W. Williams
1988 J jnl
The reliability of approximate testability measures.
IEEE Des. Test
Leendert M. Huisman
1986 A* conf
SLS - a fast switch level simulator for verification and fault coverage analysis.
DAC
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
1986 A conf
TRIM : Testability Range by Ignoring the Memory.
ITC
Leendert M. Huisman, Larry Carter, Tom W. Williams
1984 J jnl
Fast Pass-Transistor Simulation for Custom MOS Circuits.
IEEE Des. Test
Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo
1984 J jnl
Using a Hardware Simulation Engine for Custom MOS Structured Designs.
IBM J. Res. Dev.
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman
1983 A* conf
Simulating pass transistor circuits using logic simulation machines.
DAC
Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo