Lee-Sup Kim - RankMe

207 papers A* 15A 18C 23Journal 107Unranked 44

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	AToM: Adaptive Token Merging for Efficient Acceleration of Vision Transformer. IEEE Trans. Computers Jaekang Shin, Myeonggu Kang, Yunki Han, Junyoung Park, Lee-Sup Kim
2025	A*	`conf`	EOD: Enabling Low Latency GNN Inference via Near-Memory Concatenate Aggregation. ISCA Taehwan Kim, Yunki Han, Seohye Ha, Jiwan Kim, Lee-Sup Kim
2025	A*	`conf`	FLAG: An FPGA-Based System for Low-Latency GNN Inference Service Using Vector Quantization. DAC Yunki Han, Taehwan Kim, Jiwan Kim, Seohye Ha, Lee-Sup Kim
2025	A	`conf`	SAFF: Scalable Acceleration of GNN-based Machine Learning Force Fields using Tensor-Aware Hardware for Molecular Simulation. ICCAD Seohye Ha, Yunki Han, Taehwan Kim, Jiwan Kim, Junyoung Park, Gunhee Park, Lee-Sup Kim
2024	J	`jnl`	ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks. IEEE Trans. Computers Hyeonuk Kim, Youngbeom Jung, Lee-Sup Kim
2024	J	`jnl`	Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications. IEEE Comput. Archit. Lett. Yanggon Kim, Yunki Han, Jaekang Shin, Junkyum Kim, Lee-Sup Kim
2024	A	`conf`	CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed Graph. ICCAD Yunki Han, Jaekang Shin, Gunhee Park, Lee-Sup Kim
2024	J	`jnl`	ToEx: Accelerating Generation Stage of Transformer-Based Language Models via Token-Adaptive Early Exit. IEEE Trans. Computers Myeonggu Kang, Junyoung Park, Hyein Shin, Jaekang Shin, Lee-Sup Kim
2024	A*	`conf`	Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation. DAC Junyoung Park, Myeonggu Kang, Yunki Han, Yanggon Kim, Jaekang Shin, Lee-Sup Kim
2024	J	`jnl`	Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation. CoRR Junyoung Park, Myeonggu Kang, Yunki Han, Yanggon Kim, Jaekang Shin, Lee-Sup Kim
2023	J	`jnl`	Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungkyu Choi, Jaekang Shin, Lee-Sup Kim
2023	J	`jnl`	Energy-Efficient CNN Personalized Training by Adaptive Data Reformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youngbeom Jung, Hyeonuk Kim, Seungkyu Choi, Jaekang Shin, Lee-Sup Kim
2023	J	`jnl`	Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators. IEEE Trans. Computers Hyein Shin, Myeonggu Kang, Lee-Sup Kim
2023	J	`jnl`	MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT. IEEE Trans. Computers Myeonggu Kang, Hyein Shin, Junkyum Kim, Lee-Sup Kim
2023	A*	`conf`	OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing. HPCA Junkyum Kim, Myeonggu Kang, Yunki Han, Yanggon Kim, Lee-Sup Kim
2022	J	`jnl`	A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type. IEEE Trans. Computers Seungkyu Choi, Jaekang Shin, Lee-Sup Kim
2022	J	`jnl`	A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Myeonggu Kang, Hyein Shin, Lee-Sup Kim
2022	A*	`conf`	Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN. DAC Jaekang Shin, Seungkyu Choi, Jongwoo Ra, Lee-Sup Kim
2022	J	`jnl`	EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access. IEEE Trans. Computers Yunki Han, Kangkyu Park, Youngbeom Jung, Lee-Sup Kim
2022	J	`jnl`	Quantization-Error-Robust Deep Neural Network for Embedded Accelerators. IEEE Trans. Circuits Syst. II Express Briefs Youngbeom Jung, Hyeonuk Kim, Yeongjae Choi, Lee-Sup Kim
2022	J	`jnl`	Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks. IEEE Trans. Computers Kangkyu Park, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim
2022	A	`conf`	Re ICCAD Hyein Shin, Myeonggu Kang, Lee-Sup Kim
2022	J	`jnl`	S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity. IEEE Trans. Computers Myeonggu Kang, Hyeonuk Kim, Hyein Shin, Jaehyeong Sim, Kyeonghan Kim, Lee-Sup Kim
2021	A	`conf`	A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation. ICCAD Seungkyu Choi, Jaekang Shin, Lee-Sup Kim
2021	A	`conf`	A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators. ICCAD Myeonggu Kang, Hyein Shin, Jaekang Shin, Lee-Sup Kim
2021	J	`jnl`	Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks. IEEE Trans. Computers Hoseok Seol, Minhye Kim, Taesoo Kim, Yongdae Kim, Lee-Sup Kim
2021	A	`conf`	Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity. ICCAD Kangkyu Park, Yunki Han, Lee-Sup Kim
2021	A*	`conf`	Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices. DAC Hyein Shin, Myeonggu Kang, Lee-Sup Kim
2021	A*	`conf`	Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator. DAC HanCheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim
2020	J	`jnl`	A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. IEEE Trans. Circuits Syst. II Express Briefs Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim
2020	A*	`conf`	A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates. DAC Jaekang Shin, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim
2020	A	`conf`	A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration. ICCAD Hyein Shin, Myeonggu Kang, Lee-Sup Kim
2020	J	`jnl`	An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Jaehyeong Sim, Somin Lee, Lee-Sup Kim
2020	J	`jnl`	An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices. IEEE J. Solid State Circuits Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim
2020	J	`jnl`	CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim
2019	—	`conf`	A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. VLSI Circuits Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim
2019	J	`jnl`	A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. IEEE Trans. Very Large Scale Integr. Syst. Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim
2019	J	`jnl`	A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim
2019	—	`conf`	A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices. A-SSCC Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim
2019	A	`conf`	A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. ICCAD Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim
2019	A	`conf`	An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM. ICCAD Kyeonghan Kim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim
2019	A*	`conf`	An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices. DAC Seungkyu Choi, Jaekang Shin, Yeongjae Choi, Lee-Sup Kim
2019	A	`conf`	Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration. ISLPED Hyeonwook Wi, Hyeonuk Kim, Seungkyu Choi, Lee-Sup Kim
2019	J	`jnl`	DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells. IEEE Trans. Computers Jungwhan Choi, Jaemin Jang, Lee-Sup Kim
2019	A*	`conf`	NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks. HPCA Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim
2019	J	`jnl`	Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. IEEE Trans. Computers Jaemin Jang, Wongyu Shin, Jungwhan Choi, Yongju Kim, Lee-Sup Kim
2019	A	`conf`	eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators. ICCAD Youngbeom Jung, Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim
2018	J	`jnl`	A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. IEEE Trans. Circuits Syst. II Express Briefs Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim
2018	J	`jnl`	A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. IEEE Trans. Circuits Syst. II Express Briefs Yong-Hun Kim, Dongil Lee, Daewoong Lee, Lee-Sup Kim
2018	J	`jnl`	Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. IEEE Trans. Computers Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim
2018	A	`conf`	NID: processing binary convolutional neural network in commodity DRAM. ICCAD Jaehyeong Sim, Hoseok Seol, Lee-Sup Kim
2018	A	`conf`	TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training. ISLPED Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim
2017	J	`jnl`	A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. IEEE Trans. Very Large Scale Integr. Syst. Taeho Lee, Yong-Hun Kim, Lee-Sup Kim
2017	A*	`conf`	A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks. DAC Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim
2017	J	`jnl`	An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface. IEEE Trans. Circuits Syst. I Regul. Pap. Yong-Hun Kim, Taeho Lee, Hyun-Kyu Jeon, Dongil Lee, Lee-Sup Kim
2017	J	`jnl`	Bank-Group Level Parallelism. IEEE Trans. Computers Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2017	J	`jnl`	Energy-Efficient Design of Processing Element for Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Yeongjae Choi, Dongmyung Bae, Jaehyeong Sim, Seungkyu Choi, Minhye Kim, Lee-Sup Kim
2017	A	`conf`	Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph Cut in Resistor Grid. WACV Yeongjae Choi, Jun-Seok Park, Lee-Sup Kim
2017	J	`jnl`	In-DRAM Data Initialization. IEEE Trans. Very Large Scale Integr. Syst. Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2017	J	`jnl`	Rank-Level Parallelism in DRAM. IEEE Trans. Computers Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim
2017	J	`jnl`	Refresh-Aware Write Recovery Memory Controller. IEEE Trans. Computers Jaemin Jang, Wongyu Shin, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Yongju Kim, Lee-Sup Kim
2017	A	`conf`	SENIN: An energy-efficient sparse neuromorphic system with on-chip learning. ISLPED Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, Lee-Sup Kim
2016	—	`conf`	14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems. ISSCC Jaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae, Yeongjae Choi, Lee-Sup Kim
2016	J	`jnl`	A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Sang-Hye Chung, Young-Ju Kim, Yong-Hun Kim, Lee-Sup Kim
2016	J	`jnl`	A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs Dongil Lee, Taeho Lee, Young-Ju Kim, Lee-Sup Kim
2016	J	`jnl`	A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. IEEE Trans. Very Large Scale Integr. Syst. Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim
2016	J	`jnl`	A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. IEEE Trans. Very Large Scale Integr. Syst. Taeho Lee, Yong-Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim
2016	J	`jnl`	A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm. IEEE Trans. Circuits Syst. Video Technol. Jun-Seok Park, Hyo-Eun Kim, Hong-Yun Kim, Jaeyoung Lee, Lee-Sup Kim
2016	C	`conf`	Crosstalk avoidance code for direct pass-through architecture. ISCAS Minhye Kim, Soochang Chae, Young-Ju Kim, Seung-Jun Bae, Lee-Sup Kim
2016	J	`jnl`	DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. IEEE Trans. Computers Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Youngsuk Moon, Yongkee Kwon, Lee-Sup Kim
2016	A*	`conf`	Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. ISCA Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2016	J	`jnl`	Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. IEEE Trans. Computers Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim
2015	J	`jnl`	A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim
2015	J	`jnl`	A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Sang-Hye Chung, Lee-Sup Kim
2015	J	`jnl`	A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim
2015	J	`jnl`	An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yong-Hun Kim, Young-Ju Kim, Tae-Ho Lee, Lee-Sup Kim
2015	—	`conf`	An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. CICC Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim
2015	C	`conf`	An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. ISCAS Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim
2015	J	`jnl`	Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing. IEEE J. Solid State Circuits Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim
2015	A*	`conf`	Multiple clone row DRAM: a low latency and area optimized DRAM. ISCA Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim
2014	J	`jnl`	A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface. IEEE Trans. Circuits Syst. I Regul. Pap. Kyu-Dong Hwang, Lee-Sup Kim
2014	J	`jnl`	A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim
2014	J	`jnl`	A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim
2014	C	`conf`	An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO). ISCAS Wongyu Shin, Seungwook Paek, Lee-Sup Kim
2014	A*	`conf`	NUAT: A non-uniform access time memory controller. HPCA Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-Sup Kim
2014	C	`conf`	Timing error masking by exploiting operand value locality in SIMD architecture. ICCD Jaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim
2013	J	`jnl`	A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing. IEEE J. Solid State Circuits Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim
2013	J	`jnl`	A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-µm CMOS Technology. IEEE Trans. Circuits Syst. Video Technol. Jun-Seok Park, Hyo-Eun Kim, Lee-Sup Kim
2013	J	`jnl`	A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process. IEEE Trans. Circuits Syst. II Express Briefs Kyu-Dong Hwang, Lee-Sup Kim
2013	C	`conf`	A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator. ISCAS Jeongmin Yang, Young-Ju Kim, Lee-Sup Kim
2013	J	`jnl`	A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD. IEEE Trans. Circuits Syst. II Express Briefs Won-Young Lee, Jiehwan Oh, Lee-Sup Kim
2013	J	`jnl`	A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Hong-Yun Kim, Young-Jun Kim, Jiehwan Oh, Lee-Sup Kim
2013	J	`jnl`	A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. IEEE Trans. Very Large Scale Integr. Syst. Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim
2013	—	`conf`	All-digital hybrid temperature sensor network for dense thermal monitoring. ISSCC Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim
2013	—	`conf`	An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. ISSCC Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim
2013	J	`jnl`	PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwook Paek, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim
2012	—	`conf`	1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. VLSIC Sang-Hye Chung, Lee-Sup Kim
2012	—	`conf`	A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing. CICC Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim
2012	C	`conf`	A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient. ISCAS Yong-Hun Kim, Lee-Sup Kim
2012	J	`jnl`	A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. Circuits Syst. I Regul. Pap. Won-Young Lee, Lee-Sup Kim
2012	J	`jnl`	A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Won-Young Lee, Kyu-Dong Hwang, Lee-Sup Kim
2012	J	`jnl`	A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. IEEE Trans. Very Large Scale Integr. Syst. Seok-Hoon Kim, Sung-Eui Yoon, Sang-Hye Chung, Young-Jun Kim, Hong-Yun Kim, Kyusik Chung, Lee-Sup Kim
2012	J	`jnl`	A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer. IEEE Trans. Circuits Syst. Video Technol. Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim
2012	J	`jnl`	An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Won-Young Lee, Lee-Sup Kim
2012	J	`jnl`	Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders. IEEE Trans. Very Large Scale Integr. Syst. Young-Jun Kim, Hyo-Eun Kim, Seok-Hoon Kim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim
2012	J	`jnl`	MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization. IEEE J. Solid State Circuits Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim
2012	A*	`conf`	PowerField: a transient temperature-to-power technique based on Markov random field theory. DAC Seungwook Paek, Seok-Hwan Moon, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim
2011	J	`jnl`	A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. IEEE Trans. Circuits Syst. II Express Briefs Mi-Jo Kim, Lee-Sup Kim
2011	—	`conf`	A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. ISSCC Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim
2011	C	`conf`	A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. ISCAS Won-Young Lee, Lee-Sup Kim
2011	—	`conf`	A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS. CICC Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim
2011	J	`jnl`	A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. IEEE Trans. Very Large Scale Integr. Syst. Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2011	J	`jnl`	A Memory-Efficient Unified Early Z-Test. IEEE Trans. Vis. Comput. Graph. Hong-Yun Kim, Chang-Hyo Yu, Lee-Sup Kim
2011	J	`jnl`	A Spread Spectrum Clock Generator for DisplayPort Main Link. IEEE Trans. Circuits Syst. II Express Briefs Won-Young Lee, Lee-Sup Kim
2011	C	`conf`	Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors. ISCAS Seungwook Paek, Jiehwan Oh, Sang-Hye Chung, Lee-Sup Kim
2010	—	`conf`	100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. CICC Mi-Jo Kim, Lee-Sup Kim
2010	J	`jnl`	A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. IEEE J. Solid State Circuits Seok-Hoon Kim, Hong-Yun Kim, Young-Jun Kim, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
2010	J	`jnl`	A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method. IEEE Trans. Circuits Syst. II Express Briefs Hye-Yoon Joo, Lee-Sup Kim
2010	—	`conf`	A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality. ISSCC Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim
2010	C	`conf`	A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. ISCAS Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim
2010	C	`conf`	An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages. ISCAS Kyu-Dong Hwang, Lee-Sup Kim
2010	J	`jnl`	Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. IEEE J. Solid State Circuits Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim
2010	—	`conf`	Reconfigurable mobile stream processor for ray tracing. CICC Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim
2009	J	`jnl`	A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. IEEE J. Solid State Circuits Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2009	J	`jnl`	A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. IEEE Trans. Very Large Scale Integr. Syst. Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, Lee-Sup Kim
2009	J	`jnl`	A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme. IEEE J. Solid State Circuits Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim
2009	—	`conf`	A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. ISSCC Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2009	J	`jnl`	A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. IEEE J. Solid State Circuits Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho
2009	J	`jnl`	A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency. IEEE Trans. Computers Donghyun Kim, Lee-Sup Kim
2009	C	`conf`	A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link. ISCAS Won-Young Lee, Lee-Sup Kim
2009	C	`conf`	Bank-partition and Multi-fetch Scheme for Floating-point Special Function units in Multi-core Systems. ISCAS Young-Jun Kim, Kyusik Chung, Lee-Sup Kim, Seong Mo Park
2009	J	`jnl`	Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. Comput. Graph. Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2008	J	`jnl`	A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2008	J	`jnl`	A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. IEEE J. Solid State Circuits Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, Yun-Gu Lee, HyunWook Park, Jong Beom Ra, Lee-Sup Kim
2008	—	`conf`	A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. CICC Jae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu, Lee-Sup Kim
2008	—	`conf`	A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. CICC Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim
2008	J	`jnl`	An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2008	J	`jnl`	Area-efficient pixel rasterization and texture coordinate interpolation. Comput. Graph. Donghyun Kim, Lee-Sup Kim
2008	C	`conf`	Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm. ISCAS Jeong-Hyun Kim, Kyusik Chung, Young-Jun Kim, Seok-Hoon Kim, Lee-Sup Kim
2008	C	`conf`	High speed serial interface for mobile LCD driver IC. ISCAS Hyun-Kyu Jeon, Hye-Ran Kim, Jung-Min Choi, Ju-Pyo Hong, Yong-Suk Kim, Hyung-Seog Oh, Dae-Keun Han, Lee-Sup Kim
2008	J	`jnl`	Noise Robust Motion Refinement for Motion Compensated Noise Reduction. IEICE Trans. Inf. Syst. Jong-Sun Kim, Lee-Sup Kim
2008	—	`conf`	Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. CICC Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2007	—	`conf`	A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. CICC Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
2007	—	`conf`	A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. ISSCC Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, HyunWook Park, Lee-Sup Kim
2007	—	`conf`	A DLL with Jitter-Reduction Techniques for DRAM Interfaces. ISSCC Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho
2007	J	`jnl`	An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. IEEE J. Solid State Circuits Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
2007	J	`jnl`	Binary Motion Estimation with Hybrid Distortion Measure. IEICE Trans. Inf. Syst. Jong-Sun Kim, Lee-Sup Kim
2007	C	`conf`	Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. ISCAS Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2006	C	`conf`	A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver. ISCAS Ju-Pyo Hong, Kyung-Soo Ha, Lee-Sup Kim
2006	—	`conf`	A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. ISSCC Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
2006	—	`conf`	A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. ISSCC Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2006	J	`jnl`	A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. IEEE Trans. Very Large Scale Integr. Syst. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
2006	C	`conf`	A low power SoC bus with low-leakage and low-swing technique. ISCAS Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim
2006	J	`jnl`	A low-power ROM using single charge-sharing capacitor and hierarchical bit line. IEEE Trans. Very Large Scale Integr. Syst. Byung-Do Yang, Lee-Sup Kim
2006	J	`jnl`	An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. IEEE J. Solid State Circuits Donghyun Kim, Kyusik Chung, Chang-Hyo Yu, Chun-Ho Kim, Inho Lee, Jaewan Bae, Young-Jun Kim, Jae-Hyeon Park, Sungbeen Kim, Yong-Ha Park, Nak Hee Seong, Jin-Aeon Lee, Jaehong Park, Stephen Oh, Seh-Woong Jeong, Lee-Sup Kim
2006	C	`conf`	An efficient texture cache for programmable vertex shaders. ISCAS Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim
2006	C	`conf`	Charge-pump reducing current mismatch in DLLs and PLLs. ISCAS Kyung-Soo Ha, Lee-Sup Kim
2006	C	`conf`	Vertex cache of programmable geometry processor for mobile multimedia application. ISCAS Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim
2005	J	`jnl`	A 250-MHz-2-GHz wide-range delay-locked loop. IEEE J. Solid State Circuits Byung-Guk Kim, Lee-Sup Kim
2005	—	`conf`	A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. ISCAS (5) Kyusik Chung, Donghyun Kim, Lee-Sup Kim
2005	—	`conf`	A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. ISCAS (5) Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
2005	—	`conf`	A 500MHz DLL with second order duty cycle corrector for low jitter. CICC Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee
2005	J	`jnl`	A Method to Generate Soft Shadows Using a Layered Depth Image and Warping. IEEE Trans. Vis. Comput. Graph. Yeon-Ho Im, Chang-Young Han, Lee-Sup Kim
2005	J	`jnl`	A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. IEEE J. Solid State Circuits Byung-Do Yang, Lee-Sup Kim
2005	J	`jnl`	A low-power SRAM using hierarchical bit line and local sense amplifiers. IEEE J. Solid State Circuits Byung-Do Yang, Lee-Sup Kim
2005	—	`conf`	An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. ISCAS (5) Jaewan Bae, Donghyun Kim, Lee-Sup Kim
2005	J	`jnl`	An Efficient Memory Address Converter for Soc-based 3d Graphics System. J. Circuits Syst. Comput. Joung-Youn Kim, Lee-Sup Kim
2005	J	`jnl`	Geometry engine architecture with early backface culling hardware. Comput. Graph. Chang-Young Han, Yeon-Ho Im, Lee-Sup Kim
2004	—	`conf`	A 250MHz-2GHz wide range delay-locked loop. CICC Byung-Guk Kim, Lee-Sup Kim
2004	—	`conf`	A high performance low power dynamic PLA with conditional evaluation scheme. ISCAS (2) Kwang-Il Oh, Lee-Sup Kim
2004	J	`jnl`	A high-resolution synchronous mirror delay using successive approximation register. IEEE J. Solid State Circuits Kihyuk Sung, Lee-Sup Kim
2004	C	`conf`	Adaptive Selection of an Index in a Texture Cache. ICCD Chun-Ho Kim, Lee-Sup Kim
2004	J	`jnl`	An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. IEEE J. Solid State Circuits Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu
2004	J	`jnl`	An Efficient Fragment Processing Technique in A-Buffer Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Donghyun Kim, Lee-Sup Kim
2004	—	`conf`	An adaptive spatial filter for early depth test. ISCAS (2) Chang-Hyo Yu, Lee-Sup Kim
2004	—	`conf`	An error pattern ROM compression method for continuous data. ISCAS (2) Byung-Do Yang, Lee-Sup Kim
2004	—	`conf`	Division-free rasterizer for perspective-correct texture filtering. ISCAS (2) Donghyun Kim, Lee-Sup Kim
2003	—	`conf`	A PN triangle generation unit for fast and simple tessellation hardware. ISCAS (2) Kyusik Chung, Lee-Sup Kim
2003	A	`conf`	A clock delayed sleep mode domino logic for wide dynamic OR gate. ISLPED Kwang-Il Oh, Lee-Sup Kim
2003	—	`conf`	A hardware-like high-level language based environment for 3D graphics architecture exploration. ISCAS (2) Inho Lee, Joung-Youn Kim, Yeon-Ho Im, YunSeok Choi, Hyunchul Shin, Chang-Young Han, Donghyun Kim, Hyoungjoon Park, Young-Il Seo, Kyusik Chung, Chang-Hyo Yu, Kanghyup Chun, Lee-Sup Kim
2003	—	`conf`	A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter. ISCAS (2) Chang-Hyo Yu, Lee-Sup Kim
2003	—	`conf`	A low power charge sharing ROM using dummy bit lines. ISCAS (5) Byung-Do Yang, Lee-Sup Kim
2003	J	`jnl`	A low-power ROM using charge recycling and charge sharing techniques. IEEE J. Solid State Circuits Byung-Do Yang, Lee-Sup Kim
2003	J	`jnl`	A low-power charge-recycling ROM architecture. IEEE Trans. Very Large Scale Integr. Syst. Byung-Do Yang, Lee-Sup Kim
2003	J	`jnl`	Winscale: an image-scaling algorithm using an area pixel model. IEEE Trans. Circuits Syst. Video Technol. Chun-Ho Kim, Si-Mun Seong, Jin-Aeon Lee, Lee-Sup Kim
2002	—	`conf`	A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. ISCAS (1) Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim
2002	—	`conf`	A ROM compression method for continuous data. CICC Byung-Do Yang, Lee-Sup Kim
2002	—	`conf`	A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. ISCAS (5) Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
2001	J	`jnl`	A hardware cost minimized fast Phong shader. IEEE Trans. Very Large Scale Integr. Syst. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
2001	—	`conf`	A high-speed pattern decoder in MPEG-4 padding block hardware accelerator. ISCAS (2) Hyeon-Cheol Mo, Jong-Sun Kim, Lee-Sup Kim
2001	—	`conf`	A low power carry select adder with reduced area. ISCAS (4) Youngjoon Kim, Lee-Sup Kim
2001	—	`conf`	A low power charge-recycling ROM architecture. ISCAS (4) Byung-Do Yang, Lee-Sup Kim
2001	J	`jnl`	An advanced contrast enhancement using partially overlapped sub-block histogram equalization. IEEE Trans. Circuits Syst. Video Technol. Joung-Youn Kim, Lee-Sup Kim, Seung-Ho Hwang
2001	—	`conf`	Design trade-off in merged DRAM logic for video signal processing. ISCAS (5) Sunho Chang, Lee-Sup Kim
2001	—	`conf`	SPAF: Sub-texel Precision Anisotropic Filtering. Workshop on Graphics Hardware Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
2000	A	`conf`	A Memory Architecture with 4-Address Configurations for Video Signal Processing. DATE Sunho Chang, Jong-Sun Kim, Lee-Sup Kim
2000	J	`jnl`	A programmable 3.2-GOPS merged DRAM logic for video signal processing. IEEE Trans. Circuits Syst. Video Technol. Sunho Chang, Bum-Sik Kim, Lee-Sup Kim
2000	J	`jnl`	A real-time wavelet vector quantization algorithm and its VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. Seung-Kwon Paek, Lee-Sup Kim
2000	C	`conf`	An advanced contrast enhancement using partially overlapped sub-block histogram equalization. ISCAS Joung-Youn Kim, Lee-Sup Kim, Seung-Ho Hwang
2000	J	`jnl`	Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". IEEE J. Solid State Circuits Ki-Hyuk Sung, Lee-Sup Kim
2000	J	`jnl`	SPARP: a single pass antialiased rasterization processor. Comput. Graph. Jin-Aeon Lee, Lee-Sup Kim
2000	—	`conf`	Single-Pass Full-Screen Hardware Accelerated Antialiasing. Workshop on Graphics Hardware Jin-Aeon Lee, Lee-Sup Kim
1998	C	`conf`	A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics. ICCD Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
1997	A	`conf`	A new 4-2 adder and booth selector for low power MAC unit. ISLPED Bum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim
1994	J	`jnl`	A 200 MHz 13 mm IEEE J. Solid State Circuits Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai
1990	J	`jnl`	Metastability of CMOS latch/flip-flop. IEEE J. Solid State Circuits Lee-Sup Kim, Robert W. Dutton
1989	J	`jnl`	Modeling of the distributed gate RC effect in MOSFET's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lee-Sup Kim, Robert W. Dutton