Lech Józwiak - RankMe

135 papers A 1C 23Misc 1Journal 46Unranked 64

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Quality-driven design of deep neural network hardware accelerators for low power CPS and IoT applications. Microprocess. Microsystems Yahya Jan, Lech Józwiak
2023	J	`jnl`	Editorial: Recent developments and the future of Microprocess. Microsystems Lech Józwiak, Francesco Leporati
2021	—	`conf`	Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications. MECO Yahya Jan, Lech Józwiak
2018	—	`conf`	An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures. HPEC Tong Geng, Erkan Diken, Tianqi Wang, Lech Józwiak, Martin C. Herbordt
2017	J	`jnl`	Advanced mobile and wearable systems. Microprocess. Microsystems Lech Józwiak
2017	J	`jnl`	Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. Microprocess. Microsystems Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino
2017	J	`jnl`	Special issue on cyber-physical systems. Microprocess. Microsystems Radovan Stojanovic, Lech Józwiak
2016	—	`conf`	Message from the chairs. MECO Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
2016	J	`jnl`	Special Section on European Projects in Embedded System Design 2015. Microprocess. Microsystems Francesco Leporati, Lech Józwiak
2016	—	`conf`	Wearable and mobile systems. MECO Lech Józwiak
2015	—	`conf`	A compilation technique and performance profits for VLIW with heterogeneous vectors. MECO Erkan Diken, Lech Józwiak
2015	—	`conf`	FPGA-accelerated simulation engine for non-viral gene delivery. ICSPCS David Perlaza, Adam Postula, Lech Józwiak, Tadeusz A. Wysocki
2015	J	`jnl`	MICPRO special issue on European projects in embedded system design 2014. Microprocess. Microsystems Francesco Leporati, Lech Józwiak
2015	—	`conf`	Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. ASAP Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney
2014	C	`conf`	A framework for automatic custom instruction identification on multi-issue ASIPs. INDIN Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
2014	—	`conf`	Automatic complex instruction identification for efficient application mapping onto ASIPs. LASCAS Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
2014	C	`conf`	BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching. DDECS Roel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal
2014	J	`jnl`	Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. Microprocess. Microsystems Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies
2014	—	`conf`	Construction and exploitation of VLIW asips with multiple vector-widths. MECO Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal
2014	—	`conf`	Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. MECO Roel Jordans, Lech Józwiak, Henk Corporaal
2014	J	`jnl`	Preface. Microprocess. Microsystems Francesco Leporati, Lech Józwiak
2014	J	`jnl`	Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding. Microprocess. Microsystems Yahya Jan, Lech Józwiak
2013	—	`conf`	A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. ICA3PP (1) Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak, Henk Corporaal
2013	J	`jnl`	ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, Giuseppe Notarangelo
2013	C	`conf`	An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. DSD Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
2013	J	`jnl`	Application-specific processors and system-on-chips for embedded and pervasive applications. Microprocess. Microsystems Nadia Nedjah, Lech Józwiak, Luiza de Macedo Mourelle
2013	J	`jnl`	Design of massively parallel hardware multi-processors for highly-demanding embedded applications. Microprocess. Microsystems Lech Józwiak, Yahya Jan
2013	C	`conf`	Exploring processor parallelism: Estimation methods and optimization strategies. DDECS Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
2013	—	`conf`	HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. ISVLSI Lech Józwiak
2013	—	`conf`	Hardware Multi-processor Design for Highly-Demanding Applications. ITNG Lech Józwiak, Yahya Jan
2013	J	`jnl`	Hardware reuse in modern application-specific processors and accelerators. Microprocess. Microsystems Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
2013	—	`conf`	Hierarchical DSE for multi-ASIP platforms. MECO Laura Micconi, Rosilde Corvino, Deepak Gangadharan, Jan Madsen, Paul Pop, Lech Józwiak
2013	—	`conf`	Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. MECO Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
2013	—	`conf`	Message from the chairs. MECO Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
2013	J	`jnl`	Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. Microprocess. Microsystems Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
2013	J	`jnl`	Preface. Microprocess. Microsystems Francesco Leporati, Lech Józwiak
2013	—	`conf`	Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications. MECO Lech Józwiak, Jan Madsen
2013	—	`conf`	Rapid and accurate energy estimation of vector processing in VLIW ASIPs. MECO Erkan Diken, Rosilde Corvino, Lech Józwiak
2012	C	`conf`	ASAM: Automatic Architecture Synthesis and Application Mapping. DSD Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo
2012	C	`conf`	Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. DSD Roel Jordans, Rosilde Corvino, Lech Józwiak
2012	J	`jnl`	Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. VLSI Design Yahya Jan, Lech Józwiak
2012	—	`conf`	Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. ICSAMOS Rosilde Corvino, Abdoulaye Gamatié, Marc Geilen, Lech Józwiak
2012	—	`conf`	Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. VECPAR Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
2012	J	`jnl`	Scalable communication architectures for massively parallel hardware multi-processors. J. Parallel Distributed Comput. Yahya Jan, Lech Józwiak
2012	C	`conf`	Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. DSD Rosilde Corvino, Erkan Diken, Abdoulaye Gamatié, Lech Józwiak
2011	C	`conf`	A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
2011	C	`conf`	A parallel architecture for ray-tracing with an embedded intersection algorithm. ISCAS Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak
2011	—	`conf`	Advanced Architectures for Highly-demanding Embedded and Pervasive Applications. PECCS Lech Józwiak
2011	C	`conf`	Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
2011	C	`conf`	Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. PDP Lech Józwiak, Menno Lindwer
2011	—	`conf`	Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. ICA3PP (2) Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
2011	C	`conf`	Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. DSD Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz
2010	—	`conf`	Architecture Design of Reconfigurable Accelerators for Demanding Applications. ITNG Lech Józwiak, Yahya Jan
2010	J	`jnl`	Modern development methods and tools for embedded reconfigurable systems: A survey. Integr. Lech Józwiak, Nadia Nedjah, Miguel E. Figueroa
2010	—	`conf`	Quality-driven SoC architecture synthesis for embedded applications. SoCC Lech Józwiak
2010	—	`conf`	Quality-driven methodology for demanding accelerator design. ISQED Lech Józwiak, Yahya Jan
2009	—	`conf`	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. SAMOS Yahya Jan, Lech Józwiak
2009	J	`jnl`	Modern Architectures for Embedded Reconfigurable Systems - a Survey. J. Circuits Syst. Comput. Lech Józwiak, Nadia Nedjah
2009	—	`conf`	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ARC Yahya Jan, Lech Józwiak
2008	J	`jnl`	Editorial. J. Syst. Archit. Venkatesan Muthukumar, Lech Józwiak
2008	—	`conf`	Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ITNG Lech Józwiak, Alexander Douglas
2008	—	`conf`	High-Quality Circuit Synthesis for Modern Technologies. ISQED Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
2008	J	`jnl`	Quality-driven model-based architecture synthesis for real-time embedded SoCs. J. Syst. Archit. Lech Józwiak, Sien-An Ong
2008	C	`conf`	Technology Library Modelling for Information-driven Circuit Synthesis. DSD Lech Józwiak, Szymon Bieganski
2007	—	`conf`	Quality Driven Manufacturing and SOC Designs. ISQED Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak
2007	—	`conf`	Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. ISQED Lech Józwiak
2006	—	`conf`	Life-Inspired Systems and Their Quality-Driven Design. ARCS Lech Józwiak
2006	—	`conf`	Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. ICSAMOS Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
2006	C	`conf`	Multi-objective Optimal FSM State Assignment. DSD Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski
2006	C	`conf`	Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. DSD Lech Józwiak, Sien-An Ong
2005	C	`conf`	High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. DSD Lech Józwiak, Szymon Bieganski
2005	J	`jnl`	Information-driven circuit synthesis with the pre-characterized gate libraries. J. Syst. Archit. Lech Józwiak, Szymon Bieganski, Artur Chojnacki
2005	—	`conf`	Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. IWSOC Lech Józwiak
2005	—	`conf`	Plenary Session 2P. ISQED Lech Józwiak, Kaustav Banerjee
2005	J	`jnl`	Reconfigurable embedded systems: Synthesis, design and application. J. Syst. Archit. Henry Selvaraj, Lech Józwiak
2004	C	`conf`	An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. DSD Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
2004	J	`jnl`	General decomposition of incompletely specified sequential machines with multi-state behavior realization. J. Syst. Archit. Lech Józwiak, Aleksander Slusarczyk
2004	C	`conf`	Information Trans-Coders in Information-Driven Circuit Synthesis. DSD Lech Józwiak, Szymon Bieganski
2004	C	`conf`	Life-Inspired Systems. DSD Lech Józwiak
2003	J	`jnl`	Advanced AI Search Techniques in Modern Digital Circuit Synthesis. Artif. Intell. Rev. Lech Józwiak
2003	J	`jnl`	Effective and efficient FPGA synthesis through general functional decomposition. J. Syst. Archit. Lech Józwiak, Artur Chojnacki
2003	J	`jnl`	Fast and compact sequential circuits for the FPGA-based reconfigurable systems. J. Syst. Archit. Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki
2003	C	`conf`	Information-driven Library-based Circuit Synthesis. DSD Lech Józwiak, Szymon Bieganski, Artur Chojnacki
2003	J	`jnl`	Preface. J. Syst. Archit. Martyn Edwards, Lech Józwiak
2003	J	`jnl`	Special-issue on reconfigurable systems. J. Syst. Archit. Martyn Edwards, Lech Józwiak
2002	J	`jnl`	Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. J. Syst. Archit. Lech Józwiak, Adam Postula
2002	—	`conf`	Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. ISQED Aleksander Slusarczyk, Lech Józwiak
2002	J	`jnl`	Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. IEEE Micro Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
2002	J	`jnl`	Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. IEEE Micro Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
2002	J	`jnl`	Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. VLSI Design Lech Józwiak, Aleksander Slusarczyk, Marek A. Perkowski
2001	C	`conf`	Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. DSD Lech Józwiak, Artur Chojnacki
2001	C	`conf`	Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. DSD Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
2001	J	`jnl`	Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. J. Syst. Archit. Mariusz Rawski, Lech Józwiak, Tadeusz Luba
2001	—	`conf`	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. ISQED Artur Chojnacki, Lech Józwiak
2001	A	`conf`	High-quality sub-function construction in functional decomposition based on information relationship measures. DATE Lech Józwiak, Artur Chojnacki
2001	J	`jnl`	Modern methods and tools in digital system design. J. Syst. Archit. Lech Józwiak
2001	J	`jnl`	Quality-driven design in the system-on-a-chip era: Why and how? J. Syst. Archit. Lech Józwiak
2001	C	`conf`	Regular Realization of Symmetric Functions Using Reversible Logic. DSD Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
2001	J	`jnl`	Symbolic two-dimensional minimization of strongly unspecified finite state machines. J. Syst. Archit. Marek A. Perkowski, Lech Józwiak, William Zhao
2000	—	`conf`	A New State Assignment Method Targeting FPGA Implementations. EUROMICRO Lech Józwiak, Aleksander Slusarczyk
2000	—	`conf`	Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. ISMVL Artur Chojnacki, Lech Józwiak
2000	—	`conf`	Quality-Driven System-on-a-Chip Design. ISQED Lech Józwiak
1999	—	`conf`	Digital System Design: Architectures, Methods and Tools. EUROMICRO Lech Józwiak
1999	—	`conf`	Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. EUROMICRO Mariusz Rawski, Lech Józwiak, Tadeusz Luba
1999	—	`conf`	Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. EUROMICRO Lech Józwiak, Artur Chojnacki
1999	Misc	`conf`	Genetic Engineering versus Natural Evolution Genetic Algorithms with Deterministic Operators. IC-AI Lech Józwiak, Adam Postula
1999	—	`conf`	Information Relationships and Measures in Application to Logic Design. ISMVL Lech Józwiak
1999	—	`conf`	Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. EUROMICRO Torrey Lewis, Marek A. Perkowski, Lech Józwiak
1999	—	`conf`	Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. EUROMICRO Song Chen, Adam Postula, Lech Józwiak
1999	—	`conf`	Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. EUROMICRO Rafal Rzechowski, Tadeusz Luba, Lech Józwiak
1999	—	`conf`	The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. EUROMICRO Mariusz Rawski, Lech Józwiak, Tadeusz Luba
1998	—	`conf`	An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. EUROMICRO Michael Burns, Marek A. Perkowski, Lech Józwiak
1998	—	`conf`	Analysis and Synthesis of Information Systems with Information Relationships and Measures. Rough Sets and Current Trends in Computing Lech Józwiak
1998	—	`conf`	Application of the Information Measures to Input Support Selection in Functional Decomposition. Rough Sets and Current Trends in Computing Mariusz Rawski, Lech Józwiak, Artur Chojnacki
1998	—	`conf`	Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. EUROMICRO Adam Postula, Song Chen, Lech Józwiak, David Abramson
1998	—	`conf`	Design of Self-Synchronized Component FSMs for Self-Timed Systems. EUROMICRO Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak
1998	—	`conf`	Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. EUROMICRO Mariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki
1998	—	`conf`	Solving Synthesis Problems with Genetic Algorithms. EUROMICRO Lech Józwiak, Niek Ederveen, Adam Postula
1997	—	`conf`	Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
1997	—	`conf`	Decomposition of Multiple-Valued Relations . ISMVL Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
1997	—	`conf`	Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. EUROMICRO Sanof Mohamed, Marek A. Perkowski, Lech Józwiak
1997	—	`conf`	Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis. EUROMICRO Lech Józwiak
1997	—	`conf`	Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. EUROMICRO Sien-An Ong, Kari Tiensyrjä, Lech Józwiak
1997	—	`conf`	On the use of term trees for effective and efficient test pattern generation. EUROMICRO Lech Józwiak
1996	—	`conf`	Quality-Driven Decision Making Methodology for System-Level Design. EUROMICRO Lech Józwiak, Sien-An Ong
1995	J	`jnl`	Division-Based Versus General Decomposition- Based Multiple-Level Logic Synthesis. VLSI Design Frank Volf, Lech Józwiak, Mario Stevens
1995	—	`conf`	Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations. Electronic Technology Directions Lech Józwiak, Frank Wolf
1995	J	`jnl`	General Decomposition and Its Use in Digital Circuit Synthesis. VLSI Design Lech Józwiak
1995	J	`jnl`	Guest Editor's Introduction. VLSI Design Lech Józwiak
1993	J	`jnl`	Algorithms and tools for VLSI design. Microprocess. Microprogramming Lech Józwiak
1992	J	`jnl`	An Efficient Heuristic Method for State Assignment of Large Sequential Machines. J. Circuits Syst. Comput. Lech Józwiak
1992	J	`jnl`	On the use of OR-BDDs for test generation. Microprocess. Microprogramming Lech Józwiak, Hein Mijland
1991	J	`jnl`	An efficient for the sequential general decomposition of sequential machines. Microprocessing and Microprogramming Lech Józwiak, J. C. Kolsteren
1990	—	`conf`	Efficent suboptimal state assignment for large sequential machines. EURO-DAC Lech Józwiak
1990	J	`jnl`	Simultaneous decompositions of sequential machines. Microprocessing and Microprogramming Lech Józwiak