Le Ye

102 papers A* 9A 8C 16Journal 37Unranked 32
YearRankTypeTitle / Venue / Authors
2026 — conf
18.2 A 22nm 1.87ms/Frame Streaming Multi-Speaker ASR Accelerator Leveraging Contextual-Aware Redundancy Skipping with 2D-Writable Microscaling Compute-in-Memory and Similarity-Aware TCAM Design.
ISSCC
Wenjie Ren, Mingxuan Li, Zhenghao Jin, Yifan Ding, Ruohuang Xu, Xiangjun Ye, Yufei Ma, Tianyu Jia, Le Ye
2026 J jnl
A 22-nm Residual Spiking Neural Network Chip Based on Sparsity-Adaptive In-Memory Computing and a Spike-Driven Architecture.
IEEE J. Solid State Circuits
Ying Liu, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Tianyu Jia, Zhixuan Wang, Yufei Ma, Le Ye
2026 J jnl
An expansion and evolution framework of frame transformation for complex robotic systems.
Robotics Auton. Syst.
Si-Hao Zuo, Yan-Jiang Zhao, Yong-de Zhang, Le Ye
2026 J jnl
Quartet: A Digital Compute-in-Memory Versatile AI Accelerator With Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yikan Qiu, Guoxiang Li, Meng Wu, Yifan Jia, Le Ye, Yufei Ma
2025 — conf
13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction.
ISSCC
Ying Liu, Jie Li, Qining Zhang, Tianhao Zhao, Chenhao Shi, Ninghui Shang, Peiyu Chen, Xiaohuan Ge, Yufei Ma, Linxiao Shen, Zhixuan Wang, Ru Huang, Le Ye
2025 — conf
37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation.
ISSCC
Yiqi Jing, Jiaqi Zhou, Yiyang Sun, Siyuan He, Peiyu Chen, Ru Huang, Le Ye, Tianyu Jia
2025 A* conf
3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs.
DAC
Guoxiang Li, Runnan Xu, Ruohang Xu, Yikan Qiu, Renati Tuerhong, Muhan Zhang, Le Ye, Yufei Ma
2025 A* conf
3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference.
DAC
Wentao Zhao, Boya Lv, Meng Wu, Peiyu Chen, Fengyun Yan, Yufei Ma, Tianyu Jia, Ru Huang, Le Ye
2025 J jnl
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting.
IEEE J. Solid State Circuits
Siyuan Ye, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Yaohui Luan, Le Ye, Xing Zhang, Ru Huang, Linxiao Shen
2025 J jnl
A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing.
IEEE J. Solid State Circuits
Peiyu Chen, Wentao Zhao, Meng Wu, Linxiao Shen, Tianyu Jia, Ru Huang, Le Ye, Yufei Ma
2025 C conf
A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor.
ISCAS
Xueping Liu, Le Ye, Tianyu Jia
2025 J jnl
A 62.2dB SNDR Event-Driven Level-Crossing ADC With SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition.
IEEE Trans. Biomed. Circuits Syst.
Mengyu Li, Yi Huo, Shuang Song, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
2025 A* conf
Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition.
CVPR
Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, Yufei Ma
2025 J jnl
Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition.
CoRR
Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, Yufei Ma
2025 J jnl
An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS.
IEEE J. Solid State Circuits
Jihang Gao, Siyuan Ye, Jie Li, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Yaohui Luan, Ru Huang, Le Ye, Linxiao Shen
2025 A conf
CIMTester: An Agile Golden-Result-Free BIST Compiler for Robust Compute-In-Memory.
ICCAD
Wenjie Ren, Meng Wu, Mingxuan Li, Peiyu Chen, Tianyu Jia, Le Ye
2025 A* conf
EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge.
DAC
Kangbo Bai, Le Ye, Ru Huang, Tianyu Jia
2025 J jnl
EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge.
CoRR
Kangbo Bai, Le Ye, Ru Huang, Tianyu Jia
2025 — conf
GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization.
ASP-DAC
Yiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia
2025 A conf
H
ICCAD
Zizhuo Fu, Xiaotian Guo, Wenxuan Zeng, Shuzhang Zhong, Yadong Zhang, Peiyu Chen, Runsheng Wang, Le Ye, Meng Li
2025 J jnl
H2EAL: Hybrid-Bonding Architecture with Hybrid Sparse Attention for Efficient Long-Context LLM Inference.
CoRR
Zizhuo Fu, Xiaotian Guo, Wenxuan Zeng, Shuzhang Zhong, Yadong Zhang, Peiyu Chen, Runsheng Wang, Le Ye, Meng Li
2025 A conf
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs.
DATE
Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia
2025 J jnl
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs.
CoRR
Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia
2025 A* conf
Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality.
DAC
Yiyang Sun, Qinzhe Zhi, Yiqi Jing, Le Ye, Ru Huang, Tianyu Jia
2025 J jnl
Orchestrating Dual-Boundaries: An Arithmetic Intensity Inspired Acceleration Framework for Diffusion Language Models.
CoRR
Linye Wei, Wenjue Chen, Pingzhi Tang, Xiaotian Guo, Le Ye, Runsheng Wang, Meng Li
2024 — conf
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
ISSCC
Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye
2024 — conf
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.
ISSCC
Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, Ru Huang
2024 — conf
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
ISSCC
Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang
2024 — conf
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
ISSCC
Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang
2024 J jnl
A 0.39-mm
IEEE J. Solid State Circuits
Heyi Li, Kaixuan Du, Yuanxin Bao, Yanchi Dong, Jiayoon Ru, Han Xiao, Hao Zhang, Zhixuan Wang, Yi Zhong, Linxiao Shen, Le Ye, Ru Huang
2024 — conf
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup.
VLSI Technology and Circuits
Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia
2024 J jnl
A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Kaixuan Du, Maoqiang Liu, Zhixuan Wang, Heyi Li, Yuanxin Bao, Linxiao Shen, Le Ye
2024 A* conf
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration.
DAC
Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye
2024 — conf
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input.
CICC
Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye
2024 A* conf
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology.
DAC
Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang
2024 J jnl
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yufei Ma, Yikan Qiu, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang
2024 A conf
Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs.
ICCAD
Yanchi Dong, Xueping Liu, Xiaochen Hao, Yun Liang, Ru Huang, Le Ye, Tianyu Jia
2024 — conf
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow.
CICC
Yikan Qiu, Yufei Ma, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, Ru Huang
2024 — conf
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications.
CICC
Meng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye
2024 A* conf
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning.
DAC
Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia
2024 J jnl
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang, Ru Huang, Le Ye, Yufei Ma
2023 — conf
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.
ISSCC
Yihan Zhang, You You, Wenjie Ren, Xinhang Xu, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye
2023 J jnl
A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC.
IEEE J. Solid State Circuits
Zhaonan Lu, Huaikun Ji, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
2023 J jnl
A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC.
IEEE J. Solid State Circuits
Lingxin Meng, Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
2023 — conf
A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition.
ESSCIRC
Mengyu Li, Shuang Song, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
2023 — conf
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
ESSCIRC
Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye
2023 — conf
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
ISSCC
Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang
2023 J jnl
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC.
IEEE J. Solid State Circuits
Yuyan Liu, Menglian Zhao, Yibo Zhao, Xiaopeng Yu, Nianxiong Nick Tan, Le Ye, Zhichao Tan
2023 — conf
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
ISSCC
Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye
2023 — conf
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.
CICC
Ying Liu, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Oijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang
2023 A* conf
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
DAC
Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang
2023 — conf
A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications.
ASICON
Renjie Wei, Kaifeng Wang, Zhixuan Wang, Libo Yang, Fangxing Zhang, Yongqin Wu, Ye Ren, Le Ye, Lining Zhang, Weihai Bu, Ru Huang, Qianqian Huang
2023 A conf
ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions.
ICCAD
Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang
2023 J jnl
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying Liu, Yufei Ma, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye
2023 C conf
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications.
ISCAS
Yiqi Jing, Zhixuan Wang, Linxiao Shen, Yihan Zhang, Peiyu Chen, Jiayoon Ru, Le Ye
2023 A conf
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.
ISLPED
Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia
2023 — conf
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.
ESSDERC
Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang
2023 — conf
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.
ASP-DAC
Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang
2023 J jnl
Research progress on low-power artificial intelligence of things (AIoT) chip design.
Sci. China Inf. Sci.
Le Ye, Zhixuan Wang, Tianyu Jia, Yufei Ma, Linxiao Shen, Yihan Zhang, Heyi Li, Peiyu Chen, Meng Wu, Ying Liu, Yiqi Jing, Hao Zhang, Ru Huang
2022 J jnl
A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes.
Microelectron. J.
Yuanxin Bao, Le Ye
2022 — conf
A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique.
ISSCC
Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan
2022 C conf
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
ISCAS
Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye
2022 J jnl
A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers.
IEEE J. Solid State Circuits
Menglian Zhao, Yibo Zhao, Huajun Zhang, Yaopeng Hu, Yuanxin Bao, Le Ye, Wanyuan Qu, Zhichao Tan
2022 — conf
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC.
ISSCC
Yu-Yan Liu, Menglian Zhao, Yibo Zhao, Xiaopeng Yu, Nianxiong Nick Tan, Le Ye, Zhichao Tan
2022 — conf
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme.
CICC
Hao Zhang, Linxiao Shen, Shichuang Zhang, Heyi Li, Yihan Zhang, Zhichao Tan, Ru Huang, Le Ye
2022 J jnl
A power-efficient acquisition front end for the Li-ion battery management systems.
Microelectron. J.
Yuanxin Bao, Le Ye
2022 — conf
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
ISSCC
Ying Liu, Zhixuan Wang, Wei He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang
2022 A conf
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.
ICCAD
Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang
2022 C conf
Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.
ISCAS
Chang Xue, Yihan Zhang, Peiyu Chen, Mingwei Zhu, Tianqiao Wu, Meng Wu, Yandong He, Le Ye
2022 — conf
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
ISSCC
Yihan Zhang, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang
2021 — conf
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.
ISSCC
Zhixuan Wang, Le Ye, Ying Liu, Peng Zhou, Zhichao Tan, Haitao Fan, Yihan Zhang, Jiayoon Ru, Yangyuan Wang, Ru Huang
2021 — conf
5.1 A 1.5μW 0.135pJ·%RH
ISSCC
Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang
2021 J jnl
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.
IEEE J. Solid State Circuits
Zhixuan Wang, Ying Liu, Peng Zhou, Zhichao Tan, Haitao Fan, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Yangyuan Wang, Le Ye, Ru Huang
2021 — conf
A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers.
CICC
Yibo Zhao, Huajun Zhang, Yaopeng Hu, Yuanxin Bao, Le Ye, Wanyuan Qu, Menglian Zhao, Zhichao Tan
2021 J jnl
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
IEEE J. Solid State Circuits
Zhixuan Wang, Hao Zhang, Yihan Zhang, Linxiao Shen, Jiayoon Ru, Haitao Fan, Zhichao Tan, Yangyuan Wang, Le Ye, Ru Huang
2021 J jnl
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
IEEE J. Solid State Circuits
Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Linxiao Shen, Jiayoon Ru, Yihan Zhang, Le Ye, Ru Huang
2021 J jnl
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhixuan Wang, Le Ye, Qianqian Huang, Yangyuan Wang, Ru Huang
2021 A conf
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA.
FPGA
Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang
2021 J jnl
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Le Ye, Zhixuan Wang, Ying Liu, Peiyu Chen, Heyi Li, Hao Zhang, Meng Wu, Wei He, Linxiao Shen, Yihan Zhang, Zhichao Tan, Yangyuan Wang, Ru Huang
2021 J jnl
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhixuan Wang, Le Ye, Qianqian Huang, Kaixuan Du, Zhichao Tan, Yangyuan Wang, Ru Huang
2020 C conf
2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT.
ISCAS
Enbin Gong, Hao Zhang, Xiaolong Chen, Le Ye, Ru Huang
2020 — conf
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
ISSCC
Zhixuan Wang, Le Ye, Hao Zhanq, Jiayoon Ru, Haitao Fan, Yangyuan Wang, Ru Huang
2020 C conf
A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection.
ISCAS
Xiaolong Chen, Enbin Gong, Hao Zhang, Le Ye, Ru Huang
2020 J jnl
Challenges and Solutions of the TFET Circuit Design.
IEEE Trans. Circuits Syst.
Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang, Chunyu Peng, Xiulong Wu, Junning Chen
2019 C conf
Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance.
ISCAS
Zhixuan Wang, Yuan Zhong, Cheng Chen, Le Ye, Qianqian Huang, Libo Yang, Yangyuan Wang, Ru Huang
2018 C conf
Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications.
ISCAS
Libo Yang, Jiadi Zhu, Cheng Chen, Zhixuan Wang, Zexue Liu, Qianqian Huang, Le Ye, Ru Huang
2017 J jnl
A tunable transformer-based CMOS directional coupler for UHF RFID readers.
IEICE Electron. Express
Yongan Zheng, Le Ye, Xiucheng Hao, Ying Guo, Runhua Wang, Huailin Liao
2017 C conf
Benchmarking TFET from a circuit level perspective: Applications and guideline.
ISCAS
Lingyi Guo, Le Ye, Cheng Chen, Qianqian Huang, Libo Yang, Zhu Lv, Xia An, Ru Huang
2015 J jnl
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yixiao Wang, Le Ye, Huailin Liao, Ru Huang, Yangyuan Wang
2014 J jnl
A 4.2 mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Long Chen, Yixiao Wang, Chuan Wang, Jiayi Wang, Congyin Shi, Xuankai Weng, Le Ye, Junhua Liu, Huailin Liao, Yangyuan Wang
2014 C conf
A UHF RFID reader transmitter with digital CMOS power amplifier.
ISCAS
Ying Guo, Long Chen, Tao Xia, Le Ye, Xing Zhang, Huailin Liao
2013 J jnl
A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process.
Sci. China Inf. Sci.
Junhua Liu, Chen Li, Long Chen, Congyin Shi, Xuankai Weng, Yixiao Wang, Jiayi Wang, Yu Liao, Le Ye, Huailin Liao, Ru Huang
2013 J jnl
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps.
IEEE Trans. Circuits Syst. I Regul. Pap.
Le Ye, Congyin Shi, Huailin Liao, Ru Huang, Yangyuan Wang
2013 C conf
SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter.
ISCAS
Yongan Zheng, Le Ye, Long Chen, Huailin Liao, Ru Huang
2012 C conf
A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique.
ISCAS
Long Chen, Chuan Wang, Chen Li, Le Ye, Huailin Liao, Ru Huang
2012 C conf
Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads.
ISCAS
Yixiao Wang, Le Ye, Huailin Liao, Ru Huang
2012 C conf
Widely reconfigurable 8
ISCAS
Le Ye, Yixiao Wang, Long Chen, Huailin Liao, Ru Huang
2011 C conf
-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver.
ISCAS
Congyin Shi, Chuan Wang, Le Ye, Huailin Liao
2011 C conf
A 0.47mW 6
ISCAS
Le Ye, Congyin Shi, Huailin Liao, Ru Huang
2010 — conf
A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation.
ESSCIRC
Jinshu Zhao, Marcus Hellfeld, Thomas Wolf, Frank Ellinger, Le Ye
2010 J jnl
A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications.
IEEE J. Solid State Circuits
Le Ye, Huailin Liao, Fei Song, Jiang Chen, Chen Li, Jinshu Zhao, Ruiqiang Liu, Chuan Wang, Congyin Shi, Junhua Liu, Ru Huang, Yangyuan Wang
2009 — conf
A single-chip CMOS UHF RFID Reader transceiver for mobile applications.
ESSCIRC
Le Ye, Huailin Liao, Fei Song, Jiang Chen, Congyin Shi, Chen Li, Junhua Liu, Ru Huang, Jinshu Zhao, Huiling Xiao, Ruiqiang Liu, Xinan Wang