Lawrence T. Pillage

23 papers A* 9A 6C 1Journal 6Unranked 1

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
1994	A*	`conf`	A Gate-Delay Model for high-Speed CMOS Circuits. DAC Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
1994	C	`conf`	Domain Characterization of Transmission Line Models for Efficient Simulation. ICCD Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage
1994	J	`jnl`	Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
1994	J	`jnl`	Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage
1994	A*	`conf`	OTTER: Optimal Termination of Transmission Lines Excluding Radiation. DAC Rohini Gupta, Lawrence T. Pillage
1994	—	`conf`	Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
1994	A	`conf`	RC interconnect synthesis-a moment fitting approach. ICCAD Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
1994	J	`jnl`	RICE: rapid interconnect circuit evaluation using AWE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Curtis L. Ratzlaff, Lawrence T. Pillage
1994	J	`jnl`	Time-domain macromodels for VLSI interconnect analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
1993	A	`conf`	An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. ICCAD S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, Thomas L. Savarino, Dean P. Neikirk, Lawrence T. Pillage
1993	A*	`conf`	Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. DAC Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh
1993	A*	`conf`	Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage
1992	A	`conf`	AWE macromodels of VLSI interconnect for circuit simulation. ICCAD Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
1992	A	`conf`	ETA: electrical-level timing analysis. ICCAD Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage
1992	A*	`conf`	On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. DAC Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
1991	A	`conf`	Evaluating RC-Interconnect Using Moment-Matching Approximations. ICCAD Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage
1991	A*	`conf`	RICE: Rapid Interconnect Circuit Evaluator. DAC Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage
1990	J	`jnl`	Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lawrence T. Pillage, Ronald A. Rohrer
1990	A	`conf`	DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. ICCAD Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage
1989	A*	`conf`	AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. DAC Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer
1989	A*	`conf`	Efficient Final Placement Based on Nets-as-Points. DAC Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer
1988	A*	`conf`	A Quadratic Metric with a Simple Solution Scheme for Initial Placement. DAC Lawrence T. Pillage, Ronald A. Rohrer