Lawrence T. Pileggi

186 papers A* 44A 40B 4C 4Misc 2Journal 57Unranked 35

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Cyber-Resilient System Identification for Power Grid through Bayesian Integration. CoRR Shimiao Li, Guannan Qu, Bryan Hooi, Vyas Sekar, Soummya Kar, Lawrence T. Pileggi
2025	A*	`conf`	FedECADO: A Dynamical System Model of Federated Learning. ICML Aayushya Agarwal, Gauri Joshi, Lawrence T. Pileggi
2025	J	`jnl`	Integrating Forecasting Models Within Steady-State Analysis and Optimization. CoRR Aayushya Agarwal, Lawrence T. Pileggi
2025	J	`jnl`	Sparsity-exploiting Gaussian Process for Robust Transient Learning of Power System Dynamics. CoRR Tina Gao, Shimiao Li, Lawrence T. Pileggi
2025	—	`conf`	Universal Topological Arrays: An Efficient Solution for Provably Secure Hardware. ISVLSI Deepali Garg, Lawrence T. Pileggi
2024	J	`jnl`	A Hybrid Simulation of DNN-based Gray Box Models. CoRR Aayushya Agarwal, Yihan Ruan, Lawrence T. Pileggi
2024	A*	`conf`	An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. DAC Christopher Talbot, Deepali Garg, Lawrence T. Pileggi, Kenneth Mai
2024	J	`jnl`	FedECADO: A Dynamical System Model of Federated Learning. CoRR Aayushya Agarwal, Gauri Joshi, Lawrence T. Pileggi
2024	Misc	`conf`	Quantifying the Efficacy of Logic Locking Methods. VLSID Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi
2023	A*	`conf`	Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations. SP Brian Singer, Amritanshu Pandey, Shimiao Li, Lujo Bauer, Craig Miller, Lawrence T. Pileggi, Vyas Sekar
2022	J	`jnl`	Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno
2021	J	`jnl`	Quantifying the Efficacy of Logic Locking Methods. CoRR Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi
2020	J	`jnl`	A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. Samuel N. Pagliarini, Sudipta Bhuin, Mehmet Meric Isgenc, Ayan Kumar Biswas, Lawrence T. Pileggi
2020	J	`jnl`	CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi
2020	J	`jnl`	From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi
2020	—	`conf`	Latch-Based Logic Locking. HOST Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi
2020	J	`jnl`	Latch-Based Logic Locking. CoRR Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi
2020	J	`jnl`	Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi
2020	A	`conf`	Modeling Techniques for Logic Locking. ICCAD Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi
2020	J	`jnl`	Modeling Techniques for Logic Locking. CoRR Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi
2020	J	`jnl`	Securing Digital Systems via Split-Chip Obfuscation. CoRR Joseph Sweeney, Samuel Pagliarini, Lawrence T. Pileggi
2020	B	`conf`	Sensitivity Analysis of Locked Circuits. LPAR Joseph Sweeney, Marijn Heule, Lawrence T. Pileggi
2019	J	`jnl`	Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. J. Hardw. Syst. Secur. Ioannis Karageorgos, Mehmet Meric Isgenc, Samuel Pagliarini, Lawrence T. Pileggi
2019	J	`jnl`	Impact of Load Models on Power Flow Optimization. CoRR Marko Jereminov, Bryan Hooi, Amritanshu Pandey, Hyun Ah Song, Christos Faloutsos, Lawrence T. Pileggi
2018	—	`conf`	An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. ICRC Thomas C. Jackson, Samuel Pagliarini, Lawrence T. Pileggi
2018	J	`jnl`	Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes
2018	J	`jnl`	Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi
2017	—	`conf`	A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. NANOARCH Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi
2017	—	`conf`	Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi
2016	J	`jnl`	A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. Integr. Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon
2016	B	`conf`	On the design of phase locked loop oscillatory neural networks: Mitigation of transmission delay effects. IJCNN Rongye Shi, Thomas C. Jackson, Brian Swenson, Soummya Kar, Lawrence T. Pileggi
2015	—	`conf`	Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ASP-DAC Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi
2015	—	`conf`	An RRAM-based Oscillatory Neural Network. LASCAS Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi
2015	J	`jnl`	Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi
2014	—	`conf`	22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI. ISSCC Vanessa Hung-Chu Chen, Lawrence T. Pileggi
2014	J	`jnl`	A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI. IEEE J. Solid State Circuits Vanessa Hung-Chu Chen, Lawrence T. Pileggi
2014	—	`conf`	Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. MILCOM Minhee Jun, Rohit Negi, Jun Tao, Ying-Chih Wang, Shihui Yin, Tamal Mukherjee, Xin Li, Lawrence T. Pileggi
2014	J	`jnl`	Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2014	—	`conf`	Toward efficient programming of reconfigurable radio frequency (RF) receivers. ASP-DAC Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi
2013	J	`jnl`	A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012	A*	`conf`	Statistical design and optimization for adaptive post-silicon tuning of MEMS filters. DAC Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi
2011	J	`jnl`	Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi
2011	—	`conf`	Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno
2010	—	`conf`	An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi
2010	A	`conf`	Reducing variability in chip-multiprocessors with adaptive body biasing. ISLPED Alyssa Bonnoit, Lawrence T. Pileggi
2009	A*	`conf`	Creating an affordable 22nm node using design-lithography co-optimization. DAC Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
2009	A	`conf`	Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. ISLPED Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi
2009	J	`jnl`	Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd
2009	A*	`conf`	SRAM parametric failure analysis. DAC Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi
2008	—	`conf`	A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. CICC Jonathan E. Proesel, Lawrence T. Pileggi
2008	J	`jnl`	Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
2008	J	`jnl`	Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
2008	J	`jnl`	Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin Li, Yaping Zhan, Lawrence T. Pileggi
2008	—	`conf`	Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi
2007	A	`conf`	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi
2007	J	`jnl`	Asymptotic Probability Extraction for Nonnormal Performance Distributions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi
2007	A*	`conf`	Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits. DAC Xin Li, Lawrence T. Pileggi
2007	J	`jnl`	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction CoRR Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
2007	A*	`conf`	Parameterized Macromodeling for Analog System-Level Design Exploration. DAC Jian Wang, Xin Li, Lawrence T. Pileggi
2007	J	`jnl`	Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi
2006	—	`conf`	Active On-Die Suppression of Power Supply Noise. CICC Gökçe Keskin, Xin Li, Lawrence T. Pileggi
2006	A*	`conf`	Architecture-aware FPGA placement using metric embedding. DAC Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
2006	C	`conf`	Design Methodology of Regular Logic Bricks for Robust Integrated Circuits. ICCD Kim Yaw Tong, Lawrence T. Pileggi
2006	J	`jnl`	IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
2006	A*	`conf`	Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. DAC Xin Li, Jiayong Le, Lawrence T. Pileggi
2006	J	`jnl`	Statistical Performance Modeling and Optimization. Found. Trends Electron. Des. Autom. Xin Li, Jiayong Le, Lawrence T. Pileggi
2005	—	`conf`	A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators. CICC Rohan Batra, Peng Li, Lawrence T. Pileggi, Wanju Chiang
2005	J	`jnl`	Compact reduced-order modeling of weakly nonlinear analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peng Li, Lawrence T. Pileggi
2005	A*	`conf`	Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
2005	A	`conf`	Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
2005	A*	`conf`	Design methodology for IC manufacturability based on regular logic-bricks. DAC V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
2005	A	`conf`	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
2005	A*	`conf`	OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. DAC Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi
2005	A	`conf`	Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. ICCAD Xin Li, Peng Li, Lawrence T. Pileggi
2005	A	`conf`	Performance-centering optimization for system-level analog design exploration. ICCAD Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang
2005	A	`conf`	Projection-based performance modeling for inter/intra-die variations. ICCAD Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas
2005	C	`conf`	Temperature-Dependent Optimization of Cache Leakage Power Dissipation. ICCD Peng Li, Yangdong Deng, Lawrence T. Pileggi
2004	A*	`conf`	A frequency relaxation approach for analog/RF system-level simulation. DAC Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi
2004	A	`conf`	A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi
2004	A	`conf`	An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
2004	A	`conf`	Asymptotic probability extraction for non-normal distributions of circuit performance. ICCAD Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi
2004	A*	`conf`	CHIME: coupled hierarchical inductance model evaluation. DAC Satrajit Gupta, Lawrence T. Pileggi
2004	A	`conf`	Efficient full-chip thermal modeling and analysis. ICCAD Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
2004	A	`conf`	Efficient harmonic balance simulation using multi-level frequency decomposition. ICCAD Peng Li, Lawrence T. Pileggi
2004	A	`conf`	Exploring Logic Block Granularity for Regular Fabrics. DATE Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi
2004	J	`jnl`	Metal-mask configurable RF front-end circuits. IEEE J. Solid State Circuits Yang Xu, Cameron Boone, Lawrence T. Pileggi
2004	A*	`conf`	ORACLE: optimization with recourse of analog circuits including layout extraction. DAC Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
2004	J	`jnl`	Parasitics extraction with multipole refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael W. Beattie, Lawrence T. Pileggi
2004	A	`conf`	Robust analog/RF circuit design with projection-based posynomial modeling. ICCAD Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi
2004	A*	`conf`	Routing architecture exploration for regular fabrics. DAC V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
2004	A*	`conf`	STAC: statistical timing analysis with correlation. DAC Jiayong Le, Xin Li, Lawrence T. Pileggi
2003	A	`conf`	A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. ICCAD Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
2003	—	`conf`	A fast simulation approach for inductive effects of VLSI interconnects. ACM Great Lakes Symposium on VLSI Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi
2003	—	`conf`	A frequency separation macromodel for system-level simulation of RF circuits. ASP-DAC Xin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi
2003	—	`conf`	An architectural exploration of via patterned gate arrays. ISPD Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi
2003	A*	`conf`	Analog and RF circuit macromodels for system-level analysis. DAC Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi
2003	—	`conf`	Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2003	A	`conf`	Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
2003	J	`jnl`	Efficient per-nonlinearity distortion analysis for analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peng Li, Lawrence T. Pileggi
2003	J	`jnl`	Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Des. Test Comput. Hui Zheng, Byron Krauter, Lawrence T. Pileggi
2003	A*	`conf`	Exploring regular fabrics to optimize the performance-cost trade-off. DAC Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong
2003	A*	`conf`	Fast, cheap and under control: the next implementation fabric. DAC Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi
2003	J	`jnl`	Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2003	B	`conf`	Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
2003	A	`conf`	Heterogeneous Programmable Logic Block Architectures. DATE Aneesh Koorapaty, Vikas Chandra, Kim Yaw Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
2003	A*	`conf`	NORM: compact model order reduction of weakly nonlinear systems. DAC Peng Li, Lawrence T. Pileggi
2003	A	`conf`	Noise Macromodel for Radio Frequency Integrated Circuits. DATE Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
2003	—	`conf`	Nonlinear distortion analysis via linear-centric models. ASP-DAC Peng Li, Lawrence T. Pileggi
2003	—	`conf`	On-package decoupling optimization with package macromodels. CICC Hui Zheng, Byron Krauter, Lawrence T. Pileggi
2003	—	`conf`	Power Comparison of Throughput Optimized IC Busses. ISVLSI Edward Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi
2003	—	`conf`	Regular logic fabrics for a via patterned gate array (VPGA). CICC Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit
2002	A	`conf`	A Linear-Centric Modeling Approach to Harmonic Balance Analysis. DATE Peng Li, Lawrence T. Pileggi
2002	A	`conf`	A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
2002	J	`jnl`	Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. VLSI Design Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi
2002	J	`jnl`	An analysis of the wire-load model uncertainty problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
2002	A	`conf`	Congestion-Aware Logic Synthesis. DATE Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	A*	`conf`	Modeling and analysis of regular symmetrically structured power/ground distribution networks. DAC Hui Zheng, Lawrence T. Pileggi
2002	B	`conf`	Modular, Fabric-Specific Synthesis for Programmable Architectures. FPL Aneesh Koorapaty, Lawrence T. Pileggi
2002	A*	`conf`	On the efficacy of simplified 2D on-chip inductance models. DAC Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
2002	A	`conf`	On-Chip Inductance Models: 3D or Not 3D? DATE Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
2002	J	`jnl`	On-chip induction modeling: basics and advanced methods. IEEE Trans. Very Large Scale Integr. Syst. Michael W. Beattie, Lawrence T. Pileggi
2002	A	`ed.`	Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002 ICCAD Lawrence T. Pileggi, Andreas Kuehlmann
2002	A	`conf`	Robust and passive model order reduction for circuits containing susceptance elements. ICCAD Hui Zheng, Lawrence T. Pileggi
2002	J	`jnl`	TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
2002	A	`conf`	Throughput-driven IC communication fabric synthesis. ICCAD Tao Lin, Lawrence T. Pileggi
2002	—	`conf`	Time-Domain Simulation of Variational Interconnect Models. ISQED Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
2002	—	`conf`	Understanding and addressing the impact of wiring congestion during technology mapping. ISPD Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	A	`conf`	Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter
2001	—	`conf`	Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
2001	A	`conf`	Efficient inductance extraction via windowing. DATE Michael W. Beattie, Lawrence T. Pileggi
2001	J	`jnl`	Equipotential shells for efficient inductance extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi
2001	A*	`conf`	False Coupling Interactions in Static Timing Analysis. DAC Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
2001	A*	`conf`	Inductance 101: Modeling and Extraction. DAC Michael W. Beattie, Lawrence T. Pileggi
2001	J	`jnl`	Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
2001	A*	`conf`	Min/max On-Chip Inductance Models and Delay Metrics. DAC Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
2001	A*	`conf`	Modeling Magnetic Coupling for On-Chip Interconnect. DAC Michael W. Beattie, Lawrence T. Pileggi
2001	—	`conf`	Overcoming wireload model uncertainty during physical design. ISPD Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
2001	—	`conf`	RC(L) interconnect sizing with second order considerations via posynomial programming. ISPD Tao Lin, Lawrence T. Pileggi
2000	A*	`conf`	Design closure (panel session): hope or hype? DAC Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer
2000	A	`conf`	Hierarchical Interconnect Circuit Models. ICCAD Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi
2000	A*	`conf`	Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
2000	A*	`conf`	TACO: timing analysis with coupling. DAC Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
1999	A	`conf`	Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. ICCAD Michael W. Beattie, Lawrence T. Pileggi
1999	J	`jnl`	Error bounds for capacitance extraction via window techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael W. Beattie, Lawrence T. Pileggi
1999	A*	`conf`	IC Analyses Including Extracted Inductance Models. DAC Michael W. Beattie, Lawrence T. Pileggi
1999	J	`jnl`	Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Celik, Lawrence T. Pileggi
1999	A*	`conf`	Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
1999	A	`conf`	Practical considerations for passive reduction of RLC circuits. ICCAD Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1999	—	`conf`	S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1998	—	`conf`	A simple algorithm for calculating frequency-dependent inductance bounds. CICC Zhijiang He, Lawrence T. Pileggi
1998	J	`jnl`	Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. IEEE Trans. Very Large Scale Integr. Syst. Rohini Gupta, John Willis, Lawrence T. Pileggi
1998	A	`conf`	Determination of worst-case aggressor alignment for delay calculation. ICCAD Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
1998	J	`jnl`	EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rony Kay, Lawrence T. Pileggi
1998	J	`jnl`	PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1998	A*	`conf`	PRIMO: Probability Interpretation of Moments for Delay Calculation. DAC Rony Kay, Lawrence T. Pileggi
1998	A*	`conf`	TETA: Transistor-Level Engine for Timing Analysis. DAC Florentin Dartu, Lawrence T. Pileggi
1998	—	`conf`	Timing metrics for physical design of deep submicron technologies. ISPD Lawrence T. Pileggi
1998	A	`conf`	h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. ICCAD Tao Lin, Emrah Acar, Lawrence T. Pileggi
1997	A	`conf`	A hierarchical decomposition methodology for multistage clock circuits. ICCAD Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
1997	J	`jnl`	A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Noel Menezes, Ross Baldick, Lawrence T. Pileggi
1997	A*	`conf`	Bounds for BEM Capacitance Extraction. DAC Michael W. Beattie, Lawrence T. Pileggi
1997	C	`conf`	CMOS Gate Delay Models for General RLC Loading. ICCD Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
1997	A*	`conf`	Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC Florentin Dartu, Lawrence T. Pileggi
1997	C	`conf`	Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
1997	—	`conf`	EWA: exact wiring-sizing algorithm. ISPD Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
1997	J	`jnl`	Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
1997	A	`conf`	PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
1997	A*	`conf`	SPIE: Sparse Partial Inductance Extraction. DAC Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
1997	J	`jnl`	The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi
1997	J	`jnl`	Transmission line synthesis via constrained multivariable optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rohini Gupta, Byron Krauter, Lawrence T. Pileggi
1996	A*	`conf`	A Sparse Image Method for BEM Capacitance Extraction. DAC Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi
1996	A*	`conf`	An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi
1996	J	`jnl`	Domain characterization of transmission line models and analyses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi
1996	Misc	`conf`	On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. VLSI Design Rohini Gupta, Byron Krauter, Lawrence T. Pileggi
1996	J	`jnl`	Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
1996	J	`jnl`	Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
1996	A*	`conf`	RC-Interconnect Macromodels for Timing Simulation. DAC Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi
1995	A	`conf`	A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD Noel Menezes, Ross Baldick, Lawrence T. Pileggi
1995	A	`conf`	Constrained multivariable optimization of transmission lines with general topologies. ICCAD Rohini Gupta, Lawrence T. Pileggi
1995	A	`conf`	Coping with RC(L) interconnect design headaches. ICCAD Lawrence T. Pileggi
1995	A	`conf`	Generating sparse partial inductance matrices with guaranteed stability. ICCAD Byron Krauter, Lawrence T. Pileggi
1995	A*	`conf`	Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi
1995	A*	`conf`	The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. DAC Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi
1995	A*	`conf`	Transmission Line Synthesis. DAC Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi