Lawrence T. Clark

75 papers A* 2A 6C 10Misc 1Journal 35Unranked 21

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	ASAP5: A predictive PDK for the 5 nm node. Microelectron. J. Vinay Vashishtha, Lawrence T. Clark
2022	C	`conf`	Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology. ISCAS Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John S. Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella
2021	J	`jnl`	Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. Microelectron. J. Vinay Vashishtha, Lawrence T. Clark
2019	J	`jnl`	Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells. IEEE Trans. Circuits Syst. II Express Briefs John S. Brunhaver, Richard Uhrie, Lawrence T. Clark
2019	J	`jnl`	Physically Unclonable Functions Using Foundry SRAM Cells. IEEE Trans. Circuits Syst. I Regul. Pap. Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala, John S. Brunhaver
2019	J	`jnl`	Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory. Integr. Lawrence T. Clark, James Adams, Keith E. Holbert
2018	J	`jnl`	SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability. IEEE Trans. Very Large Scale Integr. Syst. Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala
2017	A	`conf`	ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper. ICCAD Vinay Vashishtha, Manoj Vangala, Lawrence T. Clark
2017	—	`conf`	Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit. MSE Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang
2017	—	`conf`	Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit. ISQED Vinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark
2017	—	`conf`	Design with sub-10 nm FinFET technologies. CICC Lawrence T. Clark, Vinay Vashishtha
2017	—	`conf`	Integrated circuit identification and true random numbers using 1.5-transistor flash memory. ISQED Lawrence T. Clark, James Adams, Keith E. Holbert
2017	C	`conf`	Robust 7-nm SRAM design on a predictive PDK. ISCAS Vinay Vashishtha, Manoj Vangala, Parv Sharma, Lawrence T. Clark
2016	J	`jnl`	ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric
2016	J	`jnl`	An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits. IEEE Trans. Computers Lawrence T. Clark, Dan W. Patterson, Chandarasekaran Ramamurthy, Keith E. Holbert
2016	J	`jnl`	SRAM-Based Unique Chip Identifier Techniques. IEEE Trans. Very Large Scale Integr. Syst. Srivatsan Chellappa, Lawrence T. Clark
2015	—	`conf`	A soft-error hardened process portable embedded microprocessor. CICC Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth
2015	—	`conf`	Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation. ISQED Srivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark
2015	C	`conf`	Delay and power tradeoffs for static and dynamic register files. ISCAS Vinay Vashishtha, Aditya Gujja, Lawrence T. Clark
2015	J	`jnl`	Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). IEEE Trans. Circuits Syst. I Regul. Pap. José M. de la Rosa, Patrick Chiang, Lawrence T. Clark
2015	C	`conf`	Simple and accurate single event charge collection macro modeling for circuit simulation. ISCAS Aymeric Privat, Lawrence T. Clark
2015	C	`conf`	Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU. ISCAS Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark
2014	—	`conf`	Independent N and P process monitors for body bias based process corner correction. CICC Lawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan
2014	—	`conf`	Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits. ISVLSI Lawrence T. Clark, Sandeep Shambhulingaiah
2014	—	`conf`	Methodology to optimize critical node separation in hardened flip-flops. ISQED Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark
2014	—	`conf`	Transient response exploration of SRAM cell metastable states caused by ionizing radiation with 3D mixed mode simulation. ICECS Aymeric Privat, Lawrence T. Clark, Hugh J. Barnaby
2013	J	`jnl`	Low Complexity Out-of-Order Issue Logic Using Static Circuits. IEEE Trans. Very Large Scale Integr. Syst. Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark
2013	—	`conf`	Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. CICC Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama
2013	J	`jnl`	Reducing Transistor Variability for High Performance Low Power Chips. IEEE Micro Robert Rogenmoser, Lawrence T. Clark
2013	A	`conf`	SRAM cell optimization for low AVT transistors. ISLPED Lawrence T. Clark, Samuel Leshner, George Tien
2011	J	`jnl`	A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing. IEEE Trans. Very Large Scale Integr. Syst. Satendra Kumar Maurya, Lawrence T. Clark
2011	J	`jnl`	A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing. J. Low Power Electron. Satendra Kumar Maurya, Lawrence T. Clark
2011	C	`conf`	Efficient voltage conversion for SRAM low standby power modes. ISCAS Lawrence T. Clark, Tai-Hua Chen, Vikas Chaudhary
2011	—	`conf`	Improved circuits for microchip identification using SRAM mismatch. CICC Srivatsan Chellappa, Aritra Dey, Lawrence T. Clark
2011	C	`conf`	Validation of and delay variation in total ionizing dose hardened standard cell libraries. ISCAS Lawrence T. Clark, David E. Pettit, Keith E. Holbert, Nathan D. Hindman
2010	C	`conf`	Fast and scalable priority encoding using static CMOS. ISCAS Satendra Kumar Maurya, Lawrence T. Clark
2010	C	`conf`	Fast low power translation lookaside buffers using hierarchical NAND match lines. ISCAS Lawrence T. Clark, Vikas Chaudhary
2010	A*	`conf`	In-situ characterization and extraction of SRAM variability. DAC Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark
2010	—	`conf`	Out-of-order issue logic using sorting networks. ACM Great Lakes Symposium on VLSI Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski
2010	—	`conf`	Single event transient mitigation in cache memory using transient error checking circuits. CICC Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert
2009	J	`jnl`	Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari
2009	A	`conf`	Low power fast and dense longest prefix match content addressable memory for IP routers. ISLPED Satendra Kumar Maurya, Lawrence T. Clark
2009	J	`jnl`	Low-Power Race-Free Programmable Logic Arrays. IEEE J. Solid State Circuits Giby Samson, Lawrence T. Clark
2009	J	`jnl`	Reducing process variation impact on replica-timed static random access memory sense timing. Integr. Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark
2008	—	`conf`	Amorphous silicon logic circuits on flexible substrates. CICC Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili
2008	J	`jnl`	Critical race-free low-power nand match line content addressable memory tagged cache memory. IET Comput. Digit. Tech. Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark
2008	J	`jnl`	High performance set associative translation lookaside buffers for low power microprocessors. Integr. Jonathan R. Haigh, Lawrence T. Clark
2008	J	`jnl`	Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Lawrence T. Clark, Ranjit Gharpurey, Payam Heydari
2008	J	`jnl`	Leakage Controlled Read Stable Static Random Access Memories. J. Comput. Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Lawrence T. Clark
2008	J	`jnl`	Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories. IEEE J. Solid State Circuits Giby Samson, Nagaraj Ananthapadmanabhan, Sayeed A. Badrudduza, Lawrence T. Clark
2007	—	`conf`	A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity. CICC Lawrence T. Clark, Mohammed Kabir, Jonathan E. Knudsen
2007	Misc	`conf`	LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. VLSI Design Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark
2007	J	`jnl`	Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Cao, Lawrence T. Clark
2007	—	`conf`	Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. CICC Sayeed A. Badrudduza, Lawrence T. Clark
2006	—	`conf`	A 0.13 μm Low-power Race-free Programmable Logic Array. CICC Giby Samson, Lawrence T. Clark
2006	J	`jnl`	An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage. IEEE J. Solid State Circuits Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen
2006	—	`conf`	Circuit architecture for low-power race-free programmable logic arrays. ACM Great Lakes Symposium on VLSI Giby Samson, Lawrence T. Clark
2006	J	`jnl`	Low-power high-performance nand match line content addressable memories. IEEE Trans. Very Large Scale Integr. Syst. Vikas Chaudhary, Lawrence T. Clark
2006	J	`jnl`	Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power. J. Low Power Electron. Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark
2006	J	`jnl`	Subthreshold to Above Threshold Level Shifter Design. J. Low Power Electron. Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark
2005	J	`jnl`	A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. IEEE J. Solid State Circuits Jonathan R. Haigh, Michael W. Wilkerson, Jay B. Miller, Timothy S. Beatty, Stephen J. Strazdus, Lawrence T. Clark
2005	J	`jnl`	Low standby power state storage for sub-130-nm technologies. IEEE J. Solid State Circuits Lawrence T. Clark, Franco Ricci, Manish Biyani
2005	A*	`conf`	Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. DAC Yu Cao, Lawrence T. Clark
2005	—	`conf`	Reducing power in flexible a-Si digital circuits while preserving state. CICC Kyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark
2005	C	`conf`	Robust Design of High Fan-In/Out Subthreshold Circuits. ICCD Jinhui Chen, Lawrence T. Clark, Yu Cao
2004	A	`conf`	Managing standby and active mode leakage power in deep sub-micron design. ISLPED Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty
2004	J	`jnl`	Reverse-body bias and supply collapse for low effective standby power. IEEE Trans. Very Large Scale Integr. Syst. Lawrence T. Clark, M. Morrow, W. Brown
2003	A	`conf`	Reducing translation lookaside buffer active power. ISLPED Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson
2003	—	`conf`	Trends and challenges for wireless embedded DSPs. CICC Lawrence T. Clark
2002	A	`conf`	Standby power management for a 0.18µm microprocessor. ISLPED Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci
2001	J	`jnl`	An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J. Solid State Circuits Lawrence T. Clark, Eric J. Hoffman, Jay B. Miller, Manish Biyani, Yuyun Liao, Stephen J. Strazdus, Michael Morrow, Kimberley E. Velarde, Mark A. Yarch
1996	J	`jnl`	High fan-in circuit design. IEEE J. Solid State Circuits Lawrence T. Clark, Gregory F. Taylor
1994	J	`jnl`	A 150 MHz 0.6 μm BiCMOS superscalar microprocessor. IEEE J. Solid State Circuits Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik
1990	J	`jnl`	VLSI Implementation of Neural Classifiers. Neural Comput. Arun Rao, Mark R. Walker, Lawrence T. Clark, Lex A. Akers, Robert O. Grondin
1989	J	`jnl`	A pipelined associated memory implemented in VLSI. IEEE J. Solid State Circuits Lawrence T. Clark, Robert O. Grondin