Laurent Sauvage

45 papers A 3B 2C 9Journal 16Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Advances in Reed-Solomon Code-Based Masking and Application to ML-KEM. IACR Commun. Cryptol. Pierre-Augustin Berthet, Yoan Rougeolle, Cédric Tavernier, Laurent Sauvage
2025	C	`conf`	Masked Vector Sampling for HQC. SECRYPT Maxime Spyropoulos, David Vigilant, Fabrice Perion, Renaud Pacalet, Laurent Sauvage
2025	J	`jnl`	Side-Channel Sensitivity Analysis on HQC: Towards a Fully Masked Implementation. IACR Cryptol. ePrint Arch. Guillaume Goy, Maxime Spyropoulos, Nicolas Aragon, Philippe Gaborit, Renaud Pacalet, Fabrice Perion, Laurent Sauvage, David Vigilant
2024	C	`conf`	EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. IOLTS Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2024	J	`jnl`	Masked Vector Sampling for HQC. IACR Cryptol. ePrint Arch. Maxime Spyropoulos, David Vigilant, Fabrice Perion, Renaud Pacalet, Laurent Sauvage
2023	C	`conf`	A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. FDTC Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2023	—	`conf`	High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA. SPACE Arnaud Varillon, Laurent Sauvage, Jean-Luc Danger
2023	A	`conf`	Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. DATE Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2023	J	`jnl`	Investigating Efficient Deep Learning Architectures For Side-Channel Attacks on AES. CoRR Yohaï-Eliel Berreby, Laurent Sauvage
2023	J	`jnl`	Quasi-linear Masking to Protect Kyber against both SCA and FIA. IACR Cryptol. ePrint Arch. Pierre-Augustin Berthet, Cédric Tavernier, Jean-Luc Danger, Laurent Sauvage
2021	—	`conf`	Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu
2020	—	`conf`	Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer. AsianHOST Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger
2019	—	`conf`	Cache-Timing Attacks Still Threaten IoT Devices. C2SI Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu
2018	—	`conf`	Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. IVSW Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi
2017	J	`jnl`	How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace. IACR Cryptol. ePrint Arch. Wei Cheng, Chao Zheng, Yuchen Cao, Yongbin Zhou, Hailong Zhang, Sylvain Guilley, Laurent Sauvage
2017	J	`jnl`	Multi-level formal verification - A new approach against fault injection attack. J. Cryptogr. Eng. Laurent Sauvage, Tarik Graba, Thibault Porteboeuf
2016	—	`conf`	Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology. Trustcom/BigDataSE/ISPA Kazuhide Fukushima, Youssef Souissi, Seira Hidano, Robert Nguyen, Jean-Luc Danger, Sylvain Guilley, Yuto Nakano, Shinsaku Kiyomoto, Laurent Sauvage
2016	C	`conf`	Differential Fault Analysis on Midori. ICICS Wei Cheng, Yongbin Zhou, Laurent Sauvage
2015	J	`jnl`	High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. CoRR Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
2015	J	`jnl`	High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. IACR Cryptol. ePrint Arch. Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
2015	—	`conf`	High precision fault injections on the instruction cache of ARMv7-M architectures. HOST Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
2014	C	`conf`	A Pre-processing Composition for Secret Key Recovery on Android Smartphone. WISTP Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Shinsaku Kiyomoto, Yutaka Miyake
2014	J	`jnl`	Hardware Trojan Horses in Cryptographic IP Cores. IACR Cryptol. ePrint Arch. Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage
2014	J	`jnl`	Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest. J. Cryptogr. Eng. Christophe Clavier, Jean-Luc Danger, Guillaume Duc, M. Abdelaziz Elaabid, Benoît Gérard, Sylvain Guilley, Annelie Heuser, Michael Kasper, Yang Li, Victor Lomné, Daisuke Nakatsu, Kazuo Ohta, Kazuo Sakiyama, Laurent Sauvage, Werner Schindler, Marc Stöttinger, Nicolas Veyrat-Charvillon, Matthieu Walle, Antoine Wurcker
2013	C	`conf`	Hardware Trojan Horses in Cryptographic IP Cores. FDTC Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage
2012	C	`conf`	A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba
2012	J	`jnl`	Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfigurable Comput. Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2011	—	`conf`	Performance evaluation of protocols resilient to physical attacks. HOST Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal
2010	—	`conf`	Cross-Correlation Cartography. ReConFig Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2010	—	`conf`	Defeating Any Secret Cryptography with SCARE Attacks. LATINCRYPT Sylvain Guilley, Laurent Sauvage, Julien Micolod, Denis Réal, Frédéric Valette
2010	J	`jnl`	Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. IEEE Trans. Computers Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
2010	J	`jnl`	Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2010	A	`conf`	Far Correlation-based EMA with a precharacterized leakage model. DATE Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage
2010	C	`conf`	Fault Injection Resilience. FDTC Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane
2010	B	`conf`	Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger
2009	—	`conf`	Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
2009	—	`conf`	DPL on Stratix II FPGA: What to Expect?. ReConFig Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
2009	J	`jnl`	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ACM Trans. Reconfigurable Technol. Syst. Laurent Sauvage, Sylvain Guilley, Yves Mathieu
2009	A	`conf`	Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar
2009	—	`conf`	Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
2008	B	`conf`	Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst
2008	—	`conf`	Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
2008	—	`conf`	Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
2008	J	`jnl`	Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
2008	C	`conf`	Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet