Laurent Fesquet

151 papers A 7B 3C 26Journal 19Unranked 95

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Microbolometer-Based Time-to-First-Spike Pixel for Infrared Imaging. ICECS Ayoub Talbi, Laurent Fesquet, Marco Passy, Skandar Basrour, Mohamed Akrarai, Mohammadreza Dolatpoor Lakeh
2025	—	`conf`	Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. SBCCI Jéssica Gonsalves Santos, Ismael de Almeida Junior, Sylvain Engels, Robin Wilson, Laurent Fesquet
2025	C	`conf`	Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF. DSD Azzadine Thajte, Sami El Amraoui, Paolo Maistri, Régis Leveugle, Giorgio Di Natale, Laurent Fesquet
2025	C	`conf`	TIMA-PUF: Time Measurement Based Arbiter PUF. IOLTS Azzadine Thajte, Laurent Fesquet, Giorgio Di Natale
2025	C	`conf`	Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. DDECS Claire Fenouillet-Béranger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudouin Martineau, Marie Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet
2024	C	`conf`	A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection. VLSI-SoC Hasan Moussa, Estelle Lauga-Larroze, Laurent Fesquet
2024	—	`conf`	Data-driven Processing Element for Sparse Convolutional Neural Networks. NewCAS Xavier Lesage, Cristiano Merio, Fernando Welzel, Luca Sauer de Araujo, Sylvain Engels, Laurent Fesquet
2024	C	`conf`	Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation. VLSI-SoC Assia El-Hadbi, Oussama Elissati, Laurent Fesquet
2024	J	`jnl`	Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. IEEE Trans. Circuits Syst. I Regul. Pap. Sana Ibrahim, Ali Al Shakoush, Serge Subias, Loic Vincent, Manuel J. Barragan Asian, Laurent Fesquet, Florence Podevin, Sylvain Bourdel
2023	—	`conf`	A Generic CDC Modeling for Data Stability Verification. ICECS Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory
2023	A	`conf`	Low-Throughput Event-Based Image Sensors and Processing. DATE Laurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stéphane Mancini, Gilles Sicard
2023	—	`conf`	Making Digital N-Path Mixers. DCIS Hasan Moussa, Jessica Gonsalves, Estelle Lauga-Larroze, Sana Ibrahim, Florence Podevin, Sylvain Bourdel, Laurent Fesquet
2023	C	`conf`	Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet
2023	J	`jnl`	Velocity and Color Estimation Using Event-Based Clustering. Sensors Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet
2022	—	`conf`	A Novel Event-Based Method for ASK Demodulation. LASCAS Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2022	—	`conf`	An improved event-by-event clustering algorithm for noisy acquisition. EBCCSP Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet
2022	—	`conf`	N-Path Mixer with Wide Rejection Including the 7 NEWCAS Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragán, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel
2022	—	`conf`	Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis. NEWCAS Hasan Moussa, Sana Ibrahim, Estelle Lauga-Larroze, Florence Podevin, Sylvain Bourdel, Laurent Fesquet
2021	C	`conf`	A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet
2021	—	`conf`	A hybrid event-based pixel for low-power image sensing. ICECS Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
2021	J	`jnl`	An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
2021	—	`conf`	An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
2021	—	`conf`	An asynchronous hybrid pixel image sensor. ASYNC Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
2021	—	`conf`	Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. EBCCSP Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2021	J	`jnl`	Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout. Sensors Enagnon Aguénounon, Safa Razavinejad, Jean-Baptiste Schell, Mohammadreza Dolatpoor Lakeh, Wassim Khaddour, Foudil Dadouche, Jean-Baptiste Kammerer, Laurent Fesquet, Wilfried Uhring
2021	—	`conf`	Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype. I2MTC Assia El-Hadbi, Oussama Elissati, Laurent Fesquet
2020	—	`conf`	A Novel Event Based Image Sensor with spacial and temporal redundancy suppression. NEWCAS Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
2020	—	`conf`	A Self-Timed Ring based PUF. ASYNC Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet
2020	—	`conf`	An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection. EBCCSP Saeed Mian Qaisar, Laurent Fesquet
2020	—	`conf`	Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression. EBCCSP Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
2020	A	`conf`	At-speed DfT Architecture for Bundled-data Design. ITC Ricardo Aquino Guazzelli, Laurent Fesquet
2020	—	`conf`	From High-Level Synthesis to Bundled-Data Circuits. SAMOS Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet
2020	—	`conf`	Improved $\pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver. NEWCAS Ali Al Shakoush, Estelle Lauga-Larroze, Florence Podevin, Sana Ibrahim, Laurent Fesquet, Sylvain Bourdel
2020	J	`jnl`	Trojan Detection Test for Clockless Circuits. J. Electron. Test. Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos
2019	C	`conf`	A Digital Event-Based Strategy for ASK demodulation. VLSI-SoC Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2019	C	`conf`	A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels
2019	—	`conf`	A new synthesis approach for non-uniform filters in the log-scale: Proof of concept. EBCCSP Brigitte Bidégaray-Fesquet, Laurent Fesquet
2019	—	`conf`	An Event-Based Strategy for ASK demodulation. EBCCSP Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2019	—	`conf`	Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet
2019	—	`conf`	From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. ASYNC Grégoire Gimenez, Jean Simatic, Laurent Fesquet
2019	—	`conf`	On-Line Adjustable Precision Computing. DTIS Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet
2019	—	`conf`	Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network. ITHET Olivier Bonnaud, Laurent Fesquet, Ahmad Bsiesy
2019	—	`conf`	Time-to-Digital Converters: A Literature Review and New Perspectives. EBCCSP Assia El-Hadbi, Oussama Elissati, Laurent Fesquet
2018	—	`conf`	A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis. ICCI*CC Raphael Frisch, Marvin Faix, Emmanuel Mazer, Laurent Fesquet, Augustin Lux
2018	—	`conf`	A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC Sophie Germain, Sylvain Engels, Laurent Fesquet
2018	J	`jnl`	A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. Microelectron. Reliab. Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos
2018	—	`conf`	An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. ICECS Timothe Turko, Wilfried Uhring, Foudil Dadouche, Laurent Fesquet
2018	J	`jnl`	Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits. Microelectron. J. Rodrigo Possamai Bastos, Leonel Acunha Guimaraes, Frank Sill Torres, Laurent Fesquet
2018	C	`conf`	Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. ISCAS Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet
2018	—	`conf`	Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet
2018	A	`conf`	Non-intrusive testing technique for detection of Trojans in asynchronous circuits. DATE Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet
2018	—	`conf`	Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet
2018	—	`conf`	Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. LASCAS Olivier Bonnaud, Laurent Fesquet, Luc Hébrard
2018	—	`conf`	Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal
2017	—	`conf`	A Bayesian Stochastic Machine for Sound Source Localization. ICRC Raphael Frisch, Raphaël Laurent, Marvin Faix, Laurent Girin, Laurent Fesquet, Augustin Lux, Jacques Droulez, Pierre Bessière, Emmanuel Mazer
2017	—	`conf`	A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. FDL (Selected Papers) Arthur Kalsing, Laurent Fesquet, Chouki Aktouf
2017	—	`conf`	A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet
2017	—	`conf`	CAR: On the highway towards de-synchronization. ICECS François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet
2017	—	`conf`	Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. ISVLSI Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet
2017	—	`conf`	Event-based design strategy for circuit electromagnetic compatibility. EBCCSP Sophie Germain, Sylvain Engels, Laurent Fesquet
2017	—	`conf`	Event-driven image sensor application: Event-driven image segmentation. EBCCSP Amani Darwish, Hassan Abbass, Laurent Fesquet, Gilles Sicard
2017	—	`conf`	High-level synthesis of an event-driven windowing process. EBCCSP Saeed Mian Qaisar, Jean Simatic, Laurent Fesquet
2017	—	`conf`	Innovative practice in the French microelectronics education targeting the industrial needs. MSE Olivier Bonnaud, Laurent Fesquet
2017	—	`conf`	On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet
2017	C	`conf`	Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. ISCAS Ali Skaf, Jean Simatic, Laurent Fesquet
2017	—	`conf`	Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet
2017	C	`conf`	Towards consistency checking between HDL and UPF descriptions. FDL Arthur Kalsing, Laurent Fesquet, Chouki Aktouf
2016	—	`conf`	Asynchronous implementation of an event-driven adaptive FIR filter. EBCCSP Taha Beyrouthy, Ahmed Roshdy, Mohammad Shukri Salman, Saeed Mian Qaisar, Laurent Fesquet
2016	—	`conf`	Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. PATMOS Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet
2016	—	`conf`	Delay partitioning helps reducing variability in 3DVLSI. ESSCIRC A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet
2016	—	`conf`	High-level synthesis for event-based systems. EBCCSP Jean Simatic, Rodrigo Possamai Bastos, Laurent Fesquet
2016	—	`conf`	Levels, peaks, slopes... which sampling for which purpose? EBCCSP Brigitte Bidégaray-Fesquet, Laurent Fesquet
2016	—	`conf`	MOOC and practices in electrical and information engineering: Complementary approaches. ITHET Olivier Bonnaud, Laurent Fesquet
2016	—	`conf`	New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet
2016	—	`conf`	Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. EWME Olivier Bonnaud, Laurent Fesquet
2016	—	`conf`	Simple tri-state logic Trojans able to upset properties of ring oscillators. DTIS Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Laurent Fesquet
2015	C	`conf`	A generic clock controller for low power systems: Experimentation on an AXI bus. VLSI-SoC Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet
2015	—	`conf`	A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing. EBCCSP Cansu Arslan, Julien Poujaud, Laurent Fesquet
2015	—	`conf`	Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications. ITHET Olivier Bonnaud, Laurent Fesquet
2015	—	`conf`	Data sampling and processing: Uniform vs. non-uniform schemes. EBCCSP Taha Beyrouthy, Laurent Fesquet, Robin Rolland
2015	J	`jnl`	Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. Microelectron. Reliab. Otto Aureliano Rolloff, Rodrigo Possamai Bastos, Laurent Fesquet
2015	—	`conf`	RTL simulation of an asynchronous reading architecture for an event-driven image sensor. EBCCSP Amani Darwish, Laurent Fesquet, Gilles Sicard
2015	—	`conf`	Towards multidisciplinarity for microelectronics education: A strategy of the French national network. MSE Olivier Bonnaud, Laurent Fesquet
2014	—	`conf`	1-Level crossing sampling scheme for low data rate image sensors. NEWCAS Amani Darwish, Laurent Fesquet, Gilles Sicard
2014	J	`jnl`	Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2014	—	`conf`	Designing ultra-low power systems with non-uniform sampling and event-driven logic. SBCCI Giuseppe Roa, Tugdual Le Pelleter, Agnès Bonvilain, Alejandro Chagoya, Laurent Fesquet
2014	—	`conf`	Distributed asynchronous controllers for clock management in low power systems. ICECS Chadi Al Khatib, Claire Aupetit, Alejandro Chagoya, Cyril Chevalier, Gilles Sicard, Laurent Fesquet
2014	—	`conf`	FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies. ITHET Olivier Bonnaud, Pascal Nouet, Laurent Fesquet, Taieb Mohammed-Brahim
2014	—	`conf`	Low data rate architecture for smart image sensor. IMSE Amani Darwish, Gilles Sicard, Laurent Fesquet
2014	—	`conf`	Self-timed rings as low-phase noise programmable oscillators. NEWCAS Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati
2014	—	`conf`	Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications. EWME Olivier Bonnaud, Laurent Fesquet
2013	—	`conf`	A Self-Timed Ring Based True Random Number Generator. ASYNC Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
2013	A	`conf`	A Very High Speed True Random Number Generator with Entropy Assessment. CHES Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert
2013	J	`jnl`	An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. Int. J. Reconfigurable Comput. Taha Beyrouthy, Laurent Fesquet
2013	—	`conf`	Empirical Recovery of Input Nonlinearity in Distributed Element Models. ALCOSP Przemyslaw Sliwinski, Krzysztof S. Berezowski, Pawel Wachel, Gilles Sicard, Laurent Fesquet
2013	—	`conf`	Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies. MSE Olivier Bonnaud, Laurent Fesquet
2013	—	`conf`	Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
2012	A	`conf`	Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
2012	—	`conf`	New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. ITHET Evelyne Excoffon, Francine Papillon, Laurent Fesquet, Ahmad Bsiesy, Olivier Bonnaud
2011	J	`jnl`	A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2011	C	`conf`	An event-driven FIR filter: Design and implementation. International Symposium on Rapid System Prototyping Taha Beyrouthy, Laurent Fesquet
2011	—	`conf`	C-elements for Hardened Self-timed Circuits. PATMOS Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
2011	J	`jnl`	Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. IEEE J. Emerg. Sel. Topics Circuits Syst. Hatem M. Zakaria, Laurent Fesquet
2011	C	`conf`	Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya
2011	—	`conf`	Formal Verification of C-element Circuits. ASYNC Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory
2010	C	`conf`	A high-speed high-resolution low-phase noise oscillator using self-timed rings. VLSI-SoC Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
2010	—	`conf`	Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
2010	J	`jnl`	IIR digital filtering of non-uniformly sampled signals via state representation. Signal Process. Laurent Fesquet, Brigitte Bidégaray-Fesquet
2010	—	`conf`	Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
2010	—	`conf`	Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet
2010	C	`conf`	Synthesis of asynchronous monitors for critical electronic systems. DDECS Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet
2010	C	`conf`	Targeting ultra-low power consumption with non-uniform sampling and filtering. ISCAS Laurent Fesquet, Gilles Sicard, Brigitte Bidégaray-Fesquet
2009	J	`jnl`	Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Signal Process. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2009	—	`conf`	Asynchronous design: A promising paradigm for electronic circuits and systems. ICECS Eslam Yahya, Laurent Fesquet
2009	J	`jnl`	Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. Very Large Scale Integr. Syst. Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
2009	—	`conf`	Controlling energy and process variability in System-on-Chips: needs for control theory. CCA/ISIC Laurent Fesquet, Hatem M. Zakaria
2009	—	`conf`	Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC Eslam Yahya, Oussama Elissati, Hatem M. Zakaria, Laurent Fesquet, Marc Renaudin
2009	C	`conf`	RAT-based formal verification of QDI asynchronous controllers. FDL Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet
2009	—	`conf`	Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
2008	J	`jnl`	A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
2008	J	`jnl`	An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. J. Electr. Comput. Eng. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2008	—	`conf`	High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ASYNC Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
2008	—	`conf`	Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2007	—	`conf`	A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
2007	—	`conf`	A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
2007	—	`conf`	Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. ICASSP (3) Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2007	C	`conf`	Asynchronous online-monitoring of logical and temporal assertions. FDL Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione
2007	—	`conf`	Computationally efficient adaptive rate sampling and filtering. EUSIPCO Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2007	J	`jnl`	FPGA Architecture for Multi-Style Asynchronous Logic CoRR N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
2006	C	`conf`	Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
2006	—	`conf`	Spectral analysis of a signal driven sampling scheme. EUSIPCO Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2006	C	`conf`	State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC Laurent Fesquet, Bertrand Folco, Mathieu Steiner, Marc Renaudin
2005	B	`conf`	A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL Laurent Fesquet, Marc Renaudin
2005	—	`conf`	Asynchronous Systems on Programmable Logic. ReCoSoC Laurent Fesquet, Jerome Quartana, Marc Renaudin
2005	A	`conf`	FPGA Architecture for Multi-Style Asynchronous Logic. DATE N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
2005	B	`conf`	GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
2005	C	`conf`	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC Jerome Quartana, Laurent Fesquet, Marc Renaudin
2005	C	`conf`	PSL-based online monitoring of digital systems. FDL D. Borionne, M. Liu, P. Ostier, Laurent Fesquet
2005	—	`ed.`	Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005 ESSCIRC Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët
2005	C	`conf`	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
2004	—	`conf`	Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
2004	J	`jnl`	La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Ann. des Télécommunications Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin
2003	—	`conf`	A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
2002	—	`conf`	Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin
2002	A	`conf`	High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
2002	B	`conf`	Implementing Asynchronous Circuits on LUT Based FPGAs. FPL Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
2002	—	`conf`	Low-Power Asynchronous A/D Conversion. PATMOS Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard
2002	—	`conf`	Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin
2001	C	`conf`	Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
1999	—	`conf`	Implementing Snoop-Coherence Protocol for Future SMP Architectures. Euro-Par Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet
1998	—	`conf`	Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. IEEE PACT Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet