Laurence E. Turner

22 papers A 1B 6C 2Misc 1Journal 2Unranked 10

Year	Rank	Type	Title / Venue / Authors
2006	—	`conf`	A C compiler for implementing FPGA based bit-serial DSP systems. FPT Dan Cyca, Laurence E. Turner
2006	—	`conf`	Bit-Serial Digital Filter Implementation using a Custom C Compiler. APCCAS Dan Cyca, Laurence E. Turner
2004	—	`conf`	A Field Programmable Bit-Serial Digital Signal Processor. IWSOC S. A. Rahim, Laurence E. Turner
2004	—	`conf`	Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm. ISCAS (5) Sean E. Krakiwsky, Laurence E. Turner, Michal M. Okoniewski
2003	J	`jnl`	A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. EURASIP J. Adv. Signal Process. Alex Carreira, Trevor W. Fox, Laurence E. Turner
2003	J	`jnl`	Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. EURASIP J. Adv. Signal Process. Trevor W. Fox, Laurence E. Turner
2003	—	`conf`	The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. IWSOC Trevor W. Fox, Alex Carreira, Laurence E. Turner
2002	B	`conf`	A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits FPL Alex Carreira, Trevor W. Fox, Laurence E. Turner
2002	—	`conf`	A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. FPT Alex Carreira, Trevor W. Fox, Laurence E. Turner
2002	A	`conf`	Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. FPGA Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski
2002	B	`conf`	Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. FPL Trevor W. Fox, Laurence E. Turner
2002	—	`conf`	Low coefficient complexity approximations of the one dimensional discrete cosine transform. ISCAS (1) Trevor W. Fox, Laurence E. Turner
2002	—	`conf`	The Automatic Generation of Application Specific Processors. IWLS S. G. Gibb, Laurence E. Turner
2001	—	`conf`	The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. ISCAS (2) Trevor W. Fox, Laurence E. Turner
1997	B	`conf`	An FPGA implementation of a matched filter detector for spread spectrum communications systems. FPL T. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, Michel Fattouche
1995	B	`conf`	BIT-Serial FIR Filters with CSD Coefficients for FPGAs. FPL Laurence E. Turner, Peter J. W. Graumann, S. G. Gibb
1995	B	`conf`	Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. FPL Gopal Panneerselvam, Peter J. W. Graumann, Laurence E. Turner
1995	B	`conf`	Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. FPL Laurence E. Turner, Peter J. W. Graumann
1994	C	`conf`	DSP System Synthesis Including Variable Data Path Width. ISCAS Bruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner
1993	C	`conf`	A method of evaluating the effects of signal quantization at arbitrary locations in recursive digital filters. ISCAS Stephen Worthington, Laurence E. Turner
1991	—	`conf`	Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. VLSI R. Nagalla, Laurence E. Turner
1984	Misc	`conf`	A bit serial LDI recursive digital filter. ICASSP Laurence E. Turner, Peter B. Denyer, David Renshaw