Laura Pozzi

90 papers A* 4A 17B 1C 5Misc 7Journal 39Unranked 17
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Improved Template for Approximate Computing.
CoRR
Morteza Rezaalipour, Francesco Costa, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi
2025 — conf
An MLIR-Based Compilation Framework for CGRA Application Deployment.
ARC
Yuxuan Wang, Cristian Tirelli, Lara Orlandic, Juan Sapriza, Rubén Rodríguez Álvarez, Giovanni Ansaloni, Laura Pozzi, David Atienza
2025 J jnl
An MLIR-based Compilation Framework for Control Flow Management on CGRAs.
CoRR
Yuxuan Wang, Cristian Tirelli, Giovanni Ansaloni, Laura Pozzi, David Atienza
2025 J jnl
Mapping code on Coarse Grained Reconfigurable Arrays using a SAT solver.
CoRR
Cristian Tirelli, Laura Pozzi
2025 A conf
Monomorphism-Based CGRA Mapping Via Space and Time Decoupling.
DATE
Cristian Tirelli, Rodrigo Otoni, Laura Pozzi
2025 J jnl
Monomorphism-based CGRA Mapping via Space and Time Decoupling.
CoRR
Cristian Tirelli, Rodrigo Otoni, Laura Pozzi
2025 J jnl
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
CoRR
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
2025 — conf
The Rise and Fall of Automatic Instruction-Set Extensions.
ASAP
Paolo Ienne, Laura Pozzi, Philip Brisk
2024 J jnl
HyperPUT: generating synthetic faulty programs to challenge bug-finding tools.
Empir. Softw. Eng.
Riccardo Felici, Laura Pozzi, Carlo A. Furia
2024 — conf
Mapping Code on Coarse Grained Reconfigurable Arrays Using a SAT Solver.
Euro-Par Workshops (2)
Cristian Tirelli, Laura Pozzi
2024 J jnl
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs.
ACM J. Emerg. Technol. Comput. Syst.
Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, José Angel Miranda, David Atienza, Laura Pozzi
2024 J jnl
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs.
CoRR
Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, José Angel Miranda Calero, David Atienza, Laura Pozzi
2024 J jnl
ShellFuzzer: Grammar-based Fuzzing of Shell Interpreters.
CoRR
Riccardo Felici, Laura Pozzi, Carlo A. Furia
2023 — conf
A Parametrizable Template for Approximate Logic Synthesis.
DSN-W
Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023 — conf
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing.
CF
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023 J jnl
Graph Neural Networks for High-Level Synthesis Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst.
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi
2023 — conf
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits.
DSN-W
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
2023 A conf
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
DATE
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
2023 — conf
SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
CF
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
2022 J jnl
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2022 J jnl
HyperPUT: Generating Synthetic Faulty Programs to Challenge Bug-Finding Tools.
CoRR
Riccardo Felici, Laura Pozzi, Carlo A. Furia
2022 A conf
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection.
DATE
Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi
2021 J jnl
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration.
CoRR
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi
2021 J jnl
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration.
IEEE Trans. Emerg. Top. Comput.
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
2021 J jnl
DB4HLS: A Database of High-Level Synthesis Design Space Explorations.
CoRR
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2021 J jnl
DB4HLS: A Database of High-Level Synthesis Design Space Explorations.
IEEE Embed. Syst. Lett.
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2021 J jnl
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems.
IEEE Trans. Computers
João M. P. Cardoso, André DeHon, Laura Pozzi
2020 J jnl
Approximate Logic Synthesis: A Survey.
Proc. IEEE
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
2020 — conf
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design.
ARC
Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi
2020 J jnl
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2019 C conf
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
ICCD
Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
2019 A* conf
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.
DAC
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
2019 J jnl
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi
2019 A conf
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors.
DATE
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin
2019 J jnl
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.
IEEE Embed. Syst. Lett.
Loris Duch, Soumya Basu, Miguel Peón-Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza
2018 Misc conf
A partitioning strategy for exploring error-resilience in circuits: work-in-progress.
CASES
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018 A conf
Circuit carving: A methodology for the design of approximate hardware.
DATE
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
2018 C conf
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.
ISCAS
Soumya Basu, Loris Duch, Miguel Peón-Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi
2018 C conf
Lattice-Traversing Design Space Exploration for High Level Synthesis.
ICCD
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
2018 — conf
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis.
HPCS
Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi
2017 J jnl
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery.
ACM Trans. Embed. Comput. Syst.
Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
2017 J jnl
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
2016 — conf
A multi-core reconfigurable architecture for ultra-low power bio-signal analysis.
BioCAS
Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi
2016 J jnl
Inexact-aware architecture design for ultra-low power bio-signal analysis.
IET Comput. Digit. Tech.
Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza
2015 J jnl
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Emanuele Giaquinta, Anadi Mishra, Laura Pozzi
2013 J jnl
An Effective Exact Algorithm and a New Upper Bound for the Number of Contacts in the Hydrophobic-Polar Two-Dimensional Lattice Model.
J. Comput. Biol.
Emanuele Giaquinta, Laura Pozzi
2012 J jnl
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt
2011 J jnl
EGRA: A Coarse Grained Reconfigurable Architectural Template.
IEEE Trans. Very Large Scale Integr. Syst.
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2011 A conf
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays.
DATE
Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt
2009 J jnl
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci.
Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2009 J jnl
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alex Orailoglu, Laura Pozzi
2009 A conf
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.
DATE
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008 Misc conf
Compiling custom instructions onto expression-grained reconfigurable architectures.
CASES
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
2008 — conf
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.
SASP
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008 J jnl
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Paolo Bonzini, Laura Pozzi
2007 — conf
A Retargetable Framework for Automated Discovery of Custom Instructions.
ASAP
Paolo Bonzini, Laura Pozzi
2007 — conf
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2007 — conf
A Study of Energy Saving in Customizable Processors.
SAMOS
Paolo Bonzini, Dilek Harmanci, Laura Pozzi
2007 A conf
A future of customizable processors: are we there yet?
DATE
Laura Pozzi, Pierre G. Paulin
2007 J jnl
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007 J jnl
Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007 A conf
Polynomial-time subgraph enumeration for automated instruction set extension.
DATE
Paolo Bonzini, Laura Pozzi
2006 A conf
Automatic identification of application-specific functional units with architecturally visible storage.
DATE
Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006 Misc conf
Code transformation strategies for extensible embedded processors.
CASES
Paolo Bonzini, Laura Pozzi
2006 A conf
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
DATE
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma
2006 J jnl
Exact and approximate algorithms for the extension of embedded processor instruction sets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Laura Pozzi, Kubilay Atasu, Paolo Ienne
2006 J jnl
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst.
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2006 Misc conf
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006 J jnl
Stream computations organized for reconfigurable execution.
Microprocess. Microsystems
André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
2006 J jnl
Virtual memory window for application-specific reconfigurable coprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2005 Misc conf
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.
CODES+ISSS
Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne
2005 Misc conf
Exploiting pipelining to relax register-file port constraints of instruction-set extensions.
CASES
Laura Pozzi, Paolo Ienne
2005 A conf
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2005 J jnl
Seamless Hardware-Software Integration in Reconfigurable Computing Systems.
IEEE Des. Test Comput.
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004 C conf
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
SCOPES
Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
2004 B conf
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.
FPL
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004 A* conf
Introduction of local memory elements in instruction set extensions.
DAC
Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
2004 A conf
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.
DATE
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
2004 — conf
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.
ASAP
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004 Misc conf
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.
FCCM
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004 A* conf
Virtual memory window for application-specific reconfigurable coprocessors.
DAC
Miljan Vuletic, Laura Pozzi, Paolo Ienne
2003 J jnl
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.
Int. J. Parallel Program.
Kubilay Atasu, Laura Pozzi, Paolo Ienne
2003 — conf
Automatic Instruction Set Extension and Utilization for Embedded Processors.
ASAP
Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
2003 A* conf
Automatic application-specific instruction-set extensions under microarchitectural constraints.
DAC
Kubilay Atasu, Laura Pozzi, Paolo Ienne
2002 A conf
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.
DATE
Laura Pozzi, Miljan Vuletic, Paolo Ienne
2001 C conf
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs.
IEEE International Workshop on Rapid System Prototyping
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
2000 A conf
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract).
FPGA
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
1999 A conf
A DAG-Based Design Approach for Reconfigurable VLIW Processors.
DATE
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
1998 A conf
Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract).
FPGA
Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami
1997 — conf
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays.
DFT
Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami