Laung-Terng Wang

61 papers A 15B 1C 2Misc 4Journal 23Unranked 15

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. IEEE Trans. Very Large Scale Integr. Syst. Dong Xiang, Xiaoqing Wen, Laung-Terng Wang
2016	J	`jnl`	CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J. Electron. Test. Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
2015	—	`conf`	SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ATS Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
2014	B	`conf`	GPU-based timing-aware test generation for small delay defects. ETS Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang
2014	J	`jnl`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2013	A	`conf`	A circular pipeline processing based deterministic parallel test pattern generator. ITC Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang
2013	J	`jnl`	LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte
2013	—	`conf`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2013	Misc	`conf`	On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
2013	J	`jnl`	Testing of Synchronizers in Asynchronous FIFO. J. Electron. Test. Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone
2012	J	`jnl`	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
2012	A	`conf`	On pinpoint capture power management in at-speed scan test generation. ITC Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2012	—	`conf`	Physical-design-friendly hierarchical logic built-in self-test - A case study. ISQED Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang
2012	J	`jnl`	Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing. ACM Trans. Design Autom. Electr. Syst. Dong Xiang, Zhen Chen, Laung-Terng Wang
2011	A	`conf`	A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
2011	—	`conf`	Luncheon Speaker: "Introduction to SoC testing". SoCC Laung-Terng Wang
2011	J	`jnl`	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
2010	Misc	`conf`	CSER: BISER-based concurrent soft-error resilience. VTS Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
2010	J	`jnl`	Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J. Electron. Test. Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
2010	J	`jnl`	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2010	—	`conf`	Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. DFT Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen
2010	—	`conf`	Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
2010	J	`jnl`	Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone
2009	—	`conf`	Analysis of Resistive Bridging Defects in a Synchronizer. Asian Test Symposium Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu
2009	—	`conf`	Analysis of Resistive Open Defects in a Synchronizer. DFT Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
2009	—	`conf`	Logic BIST Architecture for System-Level Test and Diagnosis. Asian Test Symposium Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, Feifei Zhao, Laung-Terng Wang
2009	J	`jnl`	Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008	—	`conf`	CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2008	—	`ch.`	Logic Testing. Wiley Encyclopedia of Computer Science and Engineering Laung-Terng Wang, Charles E. Stroud, Kwang-Ting (Tim) Cheng
2008	J	`jnl`	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2008	—	`conf`	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
2008	—	`conf`	Practical Challenges in Logic BIST Implementation. ATS Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami
2008	A	`conf`	Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008	J	`jnl`	VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Des. Test Comput. Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu
2007	J	`jnl`	A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2007	A	`conf`	A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
2007	—	`conf`	An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. ATS Xiaoxin Fan, Yu Hu, Laung-Terng Wang
2007	J	`jnl`	At-Speed Logic BIST for IP Cores CoRR B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu
2007	—	`conf`	Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
2006	Misc	`conf`	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2006	J	`jnl`	A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2006	A	`conf`	A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. ITC Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu
2006	J	`jnl`	A Per-Test Fault Diagnosis Method Based on the IEICE Trans. Inf. Syst. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2006	C	`conf`	Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006	—	`conf`	Test data compression based on clustered random access scan. ATS Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Huawei Li, Laung-Terng Wang, Xiaoqing Wen
2005	C	`conf`	At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
2005	A	`conf`	At-Speed Logic BIST for IP Cores. DATE B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu
2005	J	`jnl`	Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
2005	A	`conf`	Low-capture-power test generation for scan-based at-speed testing. ITC Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	Misc	`conf`	On Low-Capture-Power Test Generation for Scan Testing. VTS Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005	A	`conf`	Test compression and logic BIST at your fingertips. ITC Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu
2005	A	`conf`	UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. ITC Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang
2004	A	`conf`	On per-test fault diagnosis using the X-fault model. ICCAD Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004	A	`conf`	VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
1988	J	`jnl`	Circuits for pseudoexhaustive test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Laung-Terng Wang, Edward J. McCluskey
1988	J	`jnl`	Hybrid designs generating maximum-length sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Laung-Terng Wang, Edward J. McCluskey
1988	J	`jnl`	Linear Feedback Shift Register Design Using Cyclic Codes. IEEE Trans. Computers Laung-Terng Wang, Edward J. McCluskey
1986	A	`conf`	A Hybrid Design of Maximum-Length Sequence Generators. ITC Laung-Terng Wang, Edward J. McCluskey
1986	A	`conf`	Circuits for Pseudo-Exhaustive Test Pattern Generation. ITC Laung-Terng Wang, Edward J. McCluskey
1986	J	`jnl`	Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. IEEE Trans. Computers Laung-Terng Wang, Edward J. McCluskey
1984	A	`conf`	Self-Testing of Embedded RAMs. ITC Zuhi Sun, Laung-Terng Wang