Lasse Natvig - RankMe

52 papers A 2B 2C 6Misc 4Journal 16Unranked 22

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	FOMOsim: An open-source simulator for rigorous analysis of micromobility planning problems. Expert Syst. Appl. Steffen J. S. Bakker, Mohamed Ben Ahmed, Asbjørn Djupdal, Lasse Natvig, Henrik Andersson, Magnus Jahre, Kjetil Fagerholt
2020	J	`jnl`	Scalability analysis of AVX-512 extensions. J. Supercomput. Juan M. Cebrian, Lasse Natvig, Magnus Jahre
2018	J	`jnl`	A vectorized k-means algorithm for compressed datasets: design and experimental analysis. J. Supercomput. Abdullah Al Hasib, Juan M. Cebrian, Lasse Natvig
2018	—	`conf`	Make software harder. CF Benjamin A. Bjørnseth, Jan Christian Meyer, Lasse Natvig
2018	J	`jnl`	Proof-of-Concept Examples of Performance-Transparent Programming Models. CoRR Benjamin Andreassen Bjørnseth, Jan Christian Meyer, Lasse Natvig
2017	—	`conf`	Efficient array slicing on the Intel Xeon Phi coprocessor. ARRAY@PLDI Benjamin Andreassen Bjørnseth, Jan Christian Meyer, Lasse Natvig
2016	A	`conf`	A systematic approach to automated construction of power emulation models. DATE Benjamin A. Bjørnseth, Asbjørn Djupdal, Lasse Natvig
2016	C	`conf`	Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network. PDP Kameswar Rao Vaddina, Juan M. Cebrian, Lasse Natvig
2015	J	`jnl`	Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors. CoRR Lasse Natvig, Torbjørn Follan, Simen Støa, Sindre Magnussen, Antonio García-Guirado
2015	—	`conf`	Cost-comfort balancing in a smart residential building with bidirectional energy trading. SustainIT Abdullah Al Hasib, Nikita Nikitin, Lasse Natvig
2015	J	`jnl`	ParVec: vectorizing the PARSEC benchmark suite. Computing Juan M. Cebrian, Magnus Jahre, Lasse Natvig
2015	J	`jnl`	Tuning the victim selection policy of Intel TBB. J. Syst. Archit. Alexandru C. Iordan, Magnus Jahre, Lasse Natvig
2015	Misc	`conf`	V-PFORDelta: Data Compression for Energy Efficient Computation of Time Series. HiPC Abdullah Al Hasib, Juan M. Cebrian, Lasse Natvig
2014	C	`conf`	Load scheduling in smart buildings with bidirectional energy trading. IPCCC Abdullah Al Hasib, Nikita Nikitin, Lasse Natvig
2014	B	`conf`	Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks. ISPASS Juan M. Cebrian, Magnus Jahre, Lasse Natvig
2014	J	`jnl`	Performance and energy impact of parallelization and vectorization techniques in modern microprocessors. Computing Juan M. Cebrian, Lasse Natvig, Jan Christian Meyer
2014	—	`conf`	Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. ARCS Alexandru C. Iordan, Magnus Jahre, Lasse Natvig
2013	Misc	`conf`	Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. ICCS Alexandru C. Iordan, Magnus Jahre, Lasse Natvig
2013	—	`conf`	Energy-Efficient Sparse Matrix Autotuning with CSX - A Trade-off Study. IPDPS Workshops Jan Christian Meyer, Juan M. Cebrian, Lasse Natvig, Vasileios Karakasis, Dimitris Siakavaras, Konstantinos Nikas
2013	—	`conf`	On the energy footprint of task based parallel applications. HPCS Alexandru C. Iordan, Magnus Jahre, Lasse Natvig
2013	—	`conf`	Temperature effects on on-chip energy measurements. IGCC Juan M. Cebrian, Lasse Natvig
2012	—	`conf`	Case Studies of Multi-core Energy Efficiency in Task Based Programs. ICT-GLOW Hallgeir Lien, Lasse Natvig, Abdullah Al Hasib, Jan Christian Meyer
2012	J	`jnl`	IPM based sparse LP solver on a heterogeneous processor. Comput. Manag. Sci. Mujahed Eleyat, Lasse Natvig
2012	—	`conf`	Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors. SC Companion Juan M. Cebrian, Lasse Natvig, Jan Christian Meyer
2012	—	`conf`	Performance and Energy Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. Euro-Par Workshops Abdullah Al Hasib, Per Gunnar Kjeldsberg, Lasse Natvig
2011	J	`jnl`	A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. Magnus Jahre, Lasse Natvig
2011	C	`conf`	Cache-Aware Matrix Multiplication on Multicore Systems for IPM-based LP Solvers. FedCSIS Mujahed Eleyat, Lasse Natvig, Jørn Amundsen
2011	—	`conf`	Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. ARCS Marius Grannæs, Magnus Jahre, Lasse Natvig
2011	—	`conf`	Parallel algorithms for the maximum flow problem with minimum lot sizes. OR Mujahed Eleyat, Dag Haugland, Magnus Lie Hetland, Lasse Natvig
2011	J	`jnl`	Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. J. Instr. Level Parallelism Marius Grannæs, Magnus Jahre, Lasse Natvig
2010	J	`jnl`	Computational Computer Architecture Research at NTNU. ERCIM News Magnus Jahre, Lasse Natvig
2010	—	`conf`	DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. HiPEAC Magnus Jahre, Marius Grannæs, Lasse Natvig
2010	Misc	`conf`	Implementation of a linear programming solver on the Cell BE processor. ICCS Mujahed Eleyat, Lasse Natvig
2010	C	`conf`	Mixed-Precision Parallel Linear Programming Solver. SBAC-PAD Mujahed Eleyat, Lasse Natvig
2010	—	`conf`	Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. HiPEAC Marius Grannæs, Magnus Jahre, Lasse Natvig
2009	C	`conf`	A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. HPCC Magnus Jahre, Marius Grannæs, Lasse Natvig
2009	J	`jnl`	A compulsory yet motivating question/answer game to teach computer fundamentals. Comput. Appl. Eng. Educ. Lasse Natvig, Guttorm Sindre, Asbjørn Djupdal
2009	—	`conf`	A light-weight fairness mechanism for chip multiprocessor memory systems. Conf. Computing Frontiers Magnus Jahre, Lasse Natvig
2009	J	`jnl`	Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Trans. Educ. Guttorm Sindre, Lasse Natvig, Magnus Jahre
2008	C	`conf`	Low-cost open-page prefetch scheduling in chip multiprocessors. ICCD Marius Grannæs, Magnus Jahre, Lasse Natvig
2008	—	`conf`	Towards an Intelligent Environment for Programming Multi-core Computing Systems. Euro-Par Workshops Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa
2007	J	`jnl`	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Comput. Archit. News Haakon Dybdahl, Per Stenström, Lasse Natvig
2006	Misc	`conf`	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC Haakon Dybdahl, Per Stenström, Lasse Natvig
2006	—	`conf`	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. MEDEA@PACT Haakon Dybdahl, Per Stenström, Lasse Natvig
2006	—	`conf`	Cache Write-Back Schemes for Embedded Destructive-Read DRAM. ARCS Haakon Dybdahl, Marius Grannæs, Lasse Natvig
2006	J	`jnl`	Destructive-read in embedded DRAM, impact on power consumption. J. Embed. Comput. Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig
2006	—	`conf`	Master-Slave Tasking on Asymmetric Networks. Euro-Par Cyril Banino-Rokkones, Olivier Beaumont, Lasse Natvig
2004	B	`conf`	Age of computers: game-based teaching of computer fundamentals. ITiCSE Lasse Natvig, Steinar Line
2001	—	`conf`	Experience from a 450 Students/Year Course on Digital Logic and Computer Fundamentals using FPGAs and mu-Controllers. MSE Tormod Njølstad, Lasse Natvig
2001	—	`conf`	Simulating Parallel Architectures with BSPlab. HPCN Europe Lasse Natvig
1994	—	`conf`	Compile and Runtime Padding: An Approach to Realising Synchronous MIMD Execution. IFIP Congress (1) Lasse Natvig
1990	A	`conf`	Logarithmic time cost optimal parallel sorting is SC Lasse Natvig