Larysa Titarenko

53 papers B 1C 2Journal 16Unranked 29

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Hardware Reduction for FSMs With Extended State Codes. IEEE Access Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz
2024	J	`jnl`	Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores. Comput. Larysa Titarenko, Vyacheslav Kharchenko, Vadym Puidenko, Artem Perepelitsyn, Alexander Barkalov
2024	J	`jnl`	Reducing the number of LUTs for Mealy FSMs with state transformation. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2022	J	`jnl`	Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
2022	J	`jnl`	Improving the LUT Count for Mealy FSMS with Transformation of Output Collections. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz
2022	—	`book`	Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka
2022	J	`jnl`	Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek
2021	B	`conf`	IPNES - Interpreted Petri Net for Embedded Systems. KES Kazimierz Krzywicki, Grzegorz Andrzejewski, Wojciech Zajac, Tomasz Królikowski, Alexander Barkalov, Larysa Titarenko
2020	J	`jnl`	Improving Characteristics of LUT-Based Moore FSMs. IEEE Access Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2020	J	`jnl`	Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2020	—	`book`	Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
2019	—	`conf`	Decreasing Number of LUTs for Moore FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac
2019	—	`conf`	Design of FPGA-Based Mealy FSMs with Counters. MOCAST Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
2019	—	`conf`	Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2019	—	`conf`	Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
2019	J	`jnl`	Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. J. Circuits Syst. Comput. Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2018	—	`conf`	Design of CPLD-based mealy FSMs with counters. MOCAST Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2018	—	`conf`	Design of FPGA-based Mealy FSMs with Counters. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
2018	—	`conf`	Encoding of Terms in LUT-based Mealy FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
2018	J	`jnl`	Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2018	—	`conf`	Twofold State Assignment for LUT-based Mealy FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2018	—	`conf`	Twofold state assignment for FPGA-based mealy FSMs. MOCAST Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2017	—	`conf`	CloudBus protocol hardware multi-converter gateway for distributed embedded systems. MIXDES Kazimierz Krzywicki, Alexander Barkalov, Grzegorz Andrzejewski, Larysa Titarenko, Malgorzata Kolopienczyk
2017	—	`conf`	Code sharing in CPLD-based Moore FSMs. MOCAST Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
2017	J	`jnl`	Design of EMB-Based Moore FSMs. J. Circuits Syst. Comput. Malgorzata Kolopienczyk, Larysa Titarenko, Alexander Barkalov
2017	—	`conf`	Designing HFPGA-based FSMs with counters. MIXDES Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
2017	—	`conf`	Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
2017	—	`conf`	Designing Moore FSM with extended class codes. MOCAST Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
2014	C	`conf`	Design of Moore finite state machine with coding space stretching. HSI Larysa Titarenko, Olena Hebda, Alexander Barkalov
2014	J	`jnl`	Hardware Reduction in CPLD-Based Moore FSM. J. Circuits Syst. Comput. Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2014	C	`conf`	Hardware reduction for RAM-based Moore FSMs. HSI Malgorzata Kolopienczyk, Alexander Barkalov, Larysa Titarenko
2013	—	`conf`	Compositional Microprogram Control Unit with Operational Automaton of Transitions. PDeS Alexander Barkalov, Larysa Titarenko, Roman Babakov
2013	—	`conf`	Compositional microprogram control unit with operational automaton of transitions. EWDTS Alexander Barkalov, Roman Babakov, Larysa Titarenko
2013	—	`conf`	Design of FPGA-Based Moore FMSs with Counters. PDeS Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
2013	—	`conf`	Design of moore finite state machine with extended state codes. ITI Larysa Titarenko, Olena Hebda, Alexander Barkalov
2013	—	`conf`	EMB - Based Design of Mealy FSM. PDeS Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk
2013	J	`jnl`	Hardware Reduction in FPGA-Based Moore FSM. J. Circuits Syst. Comput. Alexander Barkalov, Larysa Titarenko, Raisa Malcheva, Kyryll Soldatov
2013	—	`conf`	Hardware reduction for compositional microprogram control unit dedicated for CPLD systems. EWDTS Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski
2013	—	`conf`	Matrix implementation of Moore FSM with nonstandard presentation of state codes. EWDTS Larysa Titarenko, Olena Hebda
2013	—	`conf`	Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. PDeS Alexander Barkalov, Slawomir Chmielewski, Larysa Titarenko
2013	—	`conf`	Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes. PDeS Larysa Titarenko, Olena Hebda, Alexander Barkalov
2011	—	`book`	Control and Adaptation in Telecommunication Systems - Mathematical Foundations Vladimir Popovskij, Alexander Barkalov, Larysa Titarenko
2011	J	`jnl`	Design of microprogrammed controllers to be implemented in FPGAs. Int. J. Appl. Math. Comput. Sci. Remigiusz Wisniewski, Alexander Barkalov, Larysa Titarenko, Wolfgang A. Halang
2011	—	`conf`	Hardware reduction for matrix circuit of control Moore automaton. EWDTS Alexander Barkalov, Larysa Titarenko, Olena Hebda
2011	—	`conf`	Optimization of microprogram control unit with code sharing. EWDTS Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski
2011	—	`conf`	Synthesis of control unit with refined state encoding for CPLD devices. EWDTS Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2010	—	`conf`	Hardware reduction for FSM - Based control units using PAL technology. EWDTS Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2010	—	`conf`	Microprogram control unit with code sharing and extended microinstruction format. EWDTS Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
2010	J	`jnl`	Reduction in the number of LUT elements for control units with code sharing. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
2010	—	`conf`	Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. EWDTS Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
2009	—	`book`	Logic Synthesis for FSM-Based Control Units Alexander Barkalov, Larysa Titarenko
2008	—	`book`	Logic Synthesis for Compositional Microprogram Control Units Alexander Barkalov, Larysa Titarenko
2007	J	`jnl`	Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski