Lars Hedrich - RankMe

64 papers A* 6A 20B 1C 10Misc 1Journal 8Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Behavioral Modeling of Analog Neural Networks Inference Circuits. SMACD Yasmine Abu-Haeyeh, Sascha Schmalhofer, Lars Hedrich
2025	A	`conf`	Formally Verifying Analog Neural Networks with Device Mismatch Variations. DATE Yasmine Abu-Haeyeh, Thomas Bartelsmeier, Tobias Ladner, Matthias Althoff, Lars Hedrich, Markus Olbrich
2025	—	`conf`	NNHC - a Neural Network to Hardware Compiler. SMACD Sascha Schmalhofer, Yasmine Abu-Haeyeh, Lars Hedrich
2024	A*	`conf`	Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. DAC Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler
2024	—	`conf`	Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction. SMACD Yasmine Abu-Haeyeh, Lars Hedrich
2024	A	`conf`	Identifying Undetectable Defects Using Equivalence Checking. ITC Lars Hedrich, Inga Abel, Jaafar Mejri, Vladimir A. Zivkovic
2023	A	`conf`	Debugging Low Power Analog Neural Networks for Edge Computing. DATE Sascha Schmalhofer, Marwin Möller, Nikoletta Katsaouni, Marcel H. Schulz, Lars Hedrich
2022	J	`jnl`	Energy efficient convolutional neural networks for arrhythmia detection. Array Nikoletta Katsaouni, Florian Aul, Lukas Krischker, Sascha Schmalhofer, Lars Hedrich, Marcel H. Schulz
2021	—	`conf`	Towards Compositional Abstraction of Analog Neuronal Networks. CCWC Ahmad Tarraf, Lars Hedrich
2020	—	`conf`	Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. ISVLSI Ahmad Tarraf, Lars Hedrich, Niklas Kochdumper, Malgorzata Rechmal-Lesse, Markus Olbrich
2020	—	`conf`	Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. ASP-DAC Niklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, Markus Olbrich, Lars Hedrich, Matthias Althoff
2020	J	`jnl`	From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction. it Inf. Technol. Ahmad Tarraf, Lars Hedrich
2019	—	`conf`	Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices. SMACD Ahmad Tarraf, Lars Hedrich
2019	A	`conf`	Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata. DATE Ahmad Tarraf, Lars Hedrich
2019	C	`conf`	Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles. ICMLA Ömer Ibrahim Erduran, Mirjam Minor, Lars Hedrich, Ahmad Tarraf, Frederik Ruehl, Hans Schroth
2019	—	`conf`	Numerical Simulations of Vibro-acoustic Behaviors related to Drive Train Assemblies. ISSE Yashwant Kolluru, Rolando Dölling, Lars Hedrich
2018	J	`jnl`	Real-time emulation of block-based analog circuits on an FPGA. Integr. Philipp Tertel, Lars Hedrich
2017	—	`conf`	Comparing code coverage metrics for analog behavioral models. SMACD Andreas Furtig, Moritz Paschke, Lars Hedrich
2017	C	`conf`	Novel metrics for Analog Mixed-Signal coverage. DDECS Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
2017	—	`conf`	Real-time emulation of block-based analog circuits on an FPGA. SMACD Philipp Tertel, Lars Hedrich
2016	A	`conf`	Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
2016	C	`conf`	Feature based state space coverage of analog circuits. FDL Andreas Furtig, Sebastian Steinhorst, Lars Hedrich
2015	J	`jnl`	A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture. Integr. Julius von Rosen, Felix Salfelder, Lars Hedrich, Benjamin Betting, Uwe Brinkschulte
2015	A	`conf`	Ageing simulation of analogue circuits and systems using adaptive transient evaluation. DATE Felix Salfelder, Lars Hedrich
2015	J	`jnl`	FEATS: Framework for Explorative Analog Topology Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Markus Meissner, Lars Hedrich
2015	—	`conf`	Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains. ISSE Tim Dackermann, Rolando Dölling, Lars Hedrich
2015	A	`conf`	Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. DATE Julius von Rosen, Markus Meissner, Lars Hedrich
2014	J	`jnl`	ASDeX: a formal specification for analog circuit enabling a full automated design validation. Des. Autom. Embed. Syst. Mingyu Ma, Lars Hedrich, Christian Sporrer
2013	—	`conf`	A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip. ARCS Benjamin Betting, Julius von Rosen, Lars Hedrich, Uwe Brinkschulte
2013	A*	`conf`	Modular system-level architecture for concurrent cell balancing. DAC Matthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich
2012	C	`conf`	Analog assertion-based verification on partial state space representations using ASL. FDL Sebastian Steinhorst, Lars Hedrich
2012	C	`conf`	Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip. ISORC Christoph Leineweber, Mathias Pacher, Benjamin Betting, Julius von Rosen, Uwe Brinkschulte, Lars Hedrich
2012	C	`conf`	Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. VLSI-SoC Sebastian Steinhorst, Lars Hedrich
2012	A	`conf`	Fast isomorphism testing for a graph-based analog circuit synthesis framework. DATE Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich
2012	A	`conf`	Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. ICCAD Sebastian Steinhorst, Lars Hedrich
2011	C	`conf`	A machine-readable specification of analog circuits for integration into a validation flow. FDL Mingyu Ma, Lars Hedrich, Christian Sporrer
2011	A	`conf`	Automated constraint-driven topology synthesis for analog circuits. DATE Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores
2011	Misc	`conf`	Design and architectures for dependable embedded systems. CODES+ISSS Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
2011	C	`conf`	Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. VLSI-SoC Oliver Mitea, Markus Meissner, Lars Hedrich
2010	J	`jnl`	Advanced methods for equivalence checking of analog circuits with strong nonlinearities. Formal Methods Syst. Des. Sebastian Steinhorst, Lars Hedrich
2010	C	`conf`	Improving verification coverage of analog circuit blocks by state space-guided transient simulation. ISCAS Sebastian Steinhorst, Lars Hedrich
2010	A	`conf`	Towards assertion-based verification of heterogeneous system designs. DATE Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich
2009	A	`conf`	Formal approaches to analog circuit verification. DATE Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang
2008	—	`conf`	A symbolic approach for mixed-signal model checking. ASP-DAC Alexander Jesser, Lars Hedrich
2008	J	`jnl`	Advanced Assertion-Based Design for Mixed-Signal Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Alexander Jesser, Stefan Lämmermann, Alexander Pacholik, Roland Weiss, Jürgen Ruf, Lars Hedrich, Wolfgang Fengler, Thomas Kropf, Wolfgang Rosenstiel
2008	A	`conf`	Model Checking of Analog Systems using an Analog Specification Language. DATE Sebastian Steinhorst, Lars Hedrich
2008	A	`conf`	Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. DATE Xiaoying Wang, Lars Hedrich
2006	—	`conf`	A case study on applying bounded model checking to analog circuit verification. MBMV Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz
2006	—	`conf`	An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. ASP-DAC Xiaoying Wang, Lars Hedrich
2006	C	`conf`	Hierarchical exploration and selection of transistor-topologies for analog circuit design. ISCAS Xiaoying Wang, Lars Hedrich
2006	—	`conf`	Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV Ralf Klausen, Lars Hedrich, Erich Barke
2005	—	`conf`	Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. FAC Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
2004	A	`conf`	Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
2002	A	`conf`	An Approach to Model Checking for Nonlinear Analog Systems. DATE Walter Hartong, Lars Hedrich, Erich Barke
2002	A	`conf`	Analog circuit sizing based on formal methods using affine arithmetic. ICCAD Andreas C. Lemke, Lars Hedrich, Erich Barke
2002	A*	`conf`	Model checking algorithms for analog verification. DAC Walter Hartong, Lars Hedrich, Erich Barke
2002	A*	`conf`	On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV Walter Hartong, Lars Hedrich, Erich Barke
2002	A	`conf`	Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
2000	A*	`conf`	A current driven routing and verification methodology for analog applications. DAC Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
1999	B	`conf`	On the Simplification of Nonlinear DAE Systems in Analog Circuit Design. CASC Tim Wichmann, Ralf Popp, Walter Hartong, Lars Hedrich
1998	A	`conf`	A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE Lars Hedrich, Erich Barke
1997	—	`—`	Ansätze zur formalen Verifikation analoger Schaltungen. Lars Hedrich
1996	A*	`conf`	Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC Carsten Borchers, Lars Hedrich, Erich Barke
1995	A	`conf`	A formal approach to nonlinear analog circuit verification. ICCAD Lars Hedrich, Erich Barke