Lars Braun

25 papers A 3B 5C 1Journal 3Unranked 11
YearRankTypeTitle / Venue / Authors
2013 — —
Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems.
Lars Braun
2012 J jnl
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices.
Int. J. Reconfigurable Comput.
Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
2011 C conf
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker.
ISCAS
Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker
2011 — conf
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA.
DASIP
Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker
2011 — conf
Dynamic Processor Reconfiguration.
ReConFig
Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker
2011 A conf
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.
DATE
Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker
2011 — conf
Run-time resource instantiation for fault tolerance in FPGAs.
AHS
Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro
2010 — ch.
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.
Dynamically Reconfigurable Systems
Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker
2010 J jnl
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems.
ACM Trans. Reconfigurable Technol. Syst.
Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
2010 — conf
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.
ISVLSI (Selected papers)
Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker
2010 — conf
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration.
ISVLSI
Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart
2010 — conf
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space.
ReConFig
Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
2010 — conf
Two Dimensional Dynamic Multigrained Reconfigurable Hardware.
ISVLSI (Selected papers)
Lars Braun, Jürgen Becker
2010 — conf
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware.
ISVLSI
Lars Braun, Jürgen Becker
2009 J jnl
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture.
J. Real Time Image Process.
Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker
2009 — conf
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
ARC
Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
2008 B conf
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
FPL
Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker
2008 A conf
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.
IPDPS
Alexander Klimm, Lars Braun, Jürgen Becker
2008 B conf
Data path driven waveform-like reconfiguration.
FPL
Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker
2008 — conf
Data reallocation by exploiting FPGA configuration mechanisms.
ARC
Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker
2008 B conf
Fine grain reconfigurable architectures.
FPL
Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008 A conf
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
IPDPS
Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker
2007 B conf
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
FPL
Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007 — conf
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
ISVLSI
Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
2004 B conf
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
FPL
Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker