Lars Bauer

118 papers A* 9A 30B 2C 1Misc 16Journal 40Unranked 17
YearRankTypeTitle / Venue / Authors
2025 A conf
Hardware/Software Co-Analysis for Worst Case Execution Time Bounds.
DATE
Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg Henkel
2025 — conf
Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems.
ASP-DAC
Hassan Nassar, Jeferson González-Gómez, Varun Manjunath, Lars Bauer, Jörg Henkel
2025 J jnl
Turbo-FHE: Accelerating Fully Homomorphic Encryption With FPGA and HBM Integration.
IEEE Des. Test
Hassan Nassar, Lars Bauer, Jörg Henkel
2024 — conf
An FPGA-Based RISC-V Instruction Set Extension and Memory Controller for Multi-Level Cell NVM.
ICM
Mina Ibrahim, Martel Shokry, Lokesh Siddhu, Lars Bauer, Hassan Nassar, Jörg Henkel
2024 J jnl
Balancing Security and Efficiency: System-Informed Mitigation of Power-Based Covert Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jeferson González-Gómez, Mohammed Bakr Sikal, Heba Khdr, Lars Bauer, Jörg Henkel
2024 — conf
Client-Server Framework for FPGA Acceleration of Fan-Vercauteren-Based Homomorphic Encryption.
ICM
Simon Bothe, Hassan Nassar, Lars Bauer, Jörg Henkel
2024 A conf
Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications.
ICCAD
Jörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei
2024 A conf
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels.
FPGA
Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel
2024 A conf
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering.
ICCAD
Hassan Nassar, Philipp Machauer, Lars Bauer, Dennis Gnad, Mehdi Baradaran Tahoori, Jörg Henkel
2024 Misc conf
HBMorphic: FHE Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA.
FCCM
Hassan Nassar, Lars Bauer, Jörg Henkel
2024 — conf
LightFAt: Mitigating Control-Flow Explosion via Lightweight PMU-Based Control-Flow Attestation.
HOST
Jeferson González-Gómez, Hassan Nassar, Lars Bauer, Jörg Henkel
2024 J jnl
LightFAt: Mitigating Control-flow Explosion via Lightweight PMU-based Control-flow Attestation.
CoRR
Jeferson González-Gómez, Hassan Nassar, Lars Bauer, Jörg Henkel
2024 J jnl
Machine-Learning-Based Side-Channel Attack Detection for FPGA SoCs.
IEEE Trans. Circuits Syst. Artif. Intell.
Lars Bauer, Hassan Nassar, Nadir Khan, Jürgen Becker, Jörg Henkel
2024 — conf
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs.
HOST
Lilas Alrahis, Hassan Nassar, Jonas Krautter, Dennis Gnad, Lars Bauer, Jörg Henkel, Mehdi B. Tahoori
2024 J jnl
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs.
CoRR
Lilas Alrahis, Hassan Nassar, Jonas Krautter, Dennis Gnad, Lars Bauer, Jörg Henkel, Mehdi B. Tahoori
2024 J jnl
MeMoir: A Software-Driven Covert Channel based on Memory Usage.
CoRR
Jeferson González-Gómez, Jose Alejandro Ibarra-Campos, Jesus Yamir Sandoval-Morales, Lars Bauer, Jörg Henkel
2024 J jnl
Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hassan Nassar, Jonas Krautter, Lars Bauer, Dennis Gnad, Mehdi B. Tahoori, Jörg Henkel
2023 J jnl
ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF.
ACM Trans. Embed. Comput. Syst.
Hassan Nassar, Lars Bauer, Jörg Henkel
2023 J jnl
Cache-Based Side-Channel Attack Mitigation for Many-Core Distributed Systems via Dynamic Task Migration.
IEEE Trans. Inf. Forensics Secur.
Jeferson González-Gómez, Lars Bauer, Jörg Henkel
2023 J jnl
Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators.
IEEE Embed. Syst. Lett.
Hassan Nassar, Lars Bauer, Jörg Henkel
2023 A* conf
Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure.
DAC
Hassan Nassar, Simon Pankner, Lars Bauer, Jörg Henkel
2023 J jnl
Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nils Hölscher, Christian Hakert, Hassan Nassar, Kuan-Hsun Chen, Lars Bauer, Jian-Jia Chen, Jörg Henkel
2023 A* conf
Smart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors.
DAC
Jeferson González-Gómez, Mohammed Bakr Sikal, Heba Khdr, Lars Bauer, Jörg Henkel
2023 Misc conf
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.
CASES
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2023 — conf
Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors.
ICM
Hassan Nassar, Rafik Youssef, Lars Bauer, Jörg Henkel
2023 J jnl
Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs.
IEEE Embed. Syst. Lett.
Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen, Jörg Henkel
2023 A conf
The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures.
DATE
Jeferson González-Gómez, Kevin Cordero-Zuñiga, Lars Bauer, Jörg Henkel
2022 J jnl
ARMOR: A Reliable and Mobility-Aware RPL for Mobile Internet of Things Infrastructures.
IEEE Internet Things J.
Ali Asghar Mohammad Salehi, Bardia Safaei, Amir Mahdi Hosseini Monazzah, Lars Bauer, Jörg Henkel, Alireza Ejlali
2022 J jnl
Agent-based Constraint Solving for Resource Allocation in Manycore Systems.
CoRR
Volker Wenzel, Lars Bauer, Wolfgang Schröder-Preikschat, Jörg Henkel
2022 J jnl
CaPUF: Cascaded PUF Structure for Machine Learning Resiliency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hassan Nassar, Lars Bauer, Jörg Henkel
2022 J jnl
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory.
ACM Trans. Embed. Comput. Syst.
Christian Hakert, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brüggen, Hussam Amrouch, Jörg Henkel, Jian-Jia Chen
2021 — ed.
Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings
ARCS
Christian Hochberger, Lars Bauer, Thilo Pionteck
2021 A conf
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs.
ICCAD
Hassan Nassar, Hanna AlZughbi, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel
2021 A conf
TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation.
DATE
Hassan Nassar, Lars Bauer, Jörg Henkel
2020 J jnl
Fast Operation Mode Selection for Highly Efficient IoT Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farzad Samie, Vasileios Tsoutsouras, Dimosthenis Masouros, Lars Bauer, Dimitrios Soudris, Jörg Henkel
2020 J jnl
Hierarchical Classification for Constrained IoT Devices: A Case Study on Human Activity Recognition.
IEEE Internet Things J.
Farzad Samie, Lars Bauer, Jörg Henkel
2020 J jnl
Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey.
IEEE Access
Bardia Safaei, Ali Asghar Mohammadsalehi, Kimia Talaei Khoosani, Saba Zarbaf, Amir Mahdi Hosseini Monazzah, Farzad Samie, Lars Bauer, Jörg Henkel, Alireza Ejlali
2020 J jnl
Improved Feature Extraction Method for Sound Recognition Applied to Automatic Sorting of Recycling Wastes.
J. Inf. Process.
Tatsuji Munaka, Farzad Samie, Lars Bauer, Jörg Henkel
2020 J jnl
SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory.
CoRR
Christian Hakert, Kuan-Hsun Chen, Paul R. Genssler, Georg von der Brüggen, Lars Bauer, Hussam Amrouch, Jian-Jia Chen, Jörg Henkel
2020 — conf
System Software for Resource Arbitration on Future Many-* Architectures.
IPDPS Workshops
Florian Schmaus, Sebastian Maier, Tobias Langer, Jonas Rabenstein, Timo Hönig, Wolfgang Schröder-Preikschat, Lars Bauer, Jörg Henkel
2019 — conf
Analyses and architectures for mixed-critical systems: industry trends and research perspective.
EMSOFT Companion
Lars Bauer, Marvin Damschen, Dirk Ziegenbein, Arne Hamann, Alessandro Biondi, Giorgio C. Buttazzo, Jörg Henkel
2019 A conf
DMRM: Distributed Market-Based Resource Management of Edge Computing Systems.
DATE
Manolis Katsaragakis, Dimosthenis Masouros, Vasileios Tsoutsouras, Farzad Samie, Lars Bauer, Jörg Henkel, Dimitrios Soudris
2019 J jnl
From Cloud Down to Things: An Overview of Machine Learning in Internet of Things.
IEEE Internet Things J.
Farzad Samie, Lars Bauer, Jörg Henkel
2019 A conf
WCET Guarantees for Opportunistic Runtime Reconfiguration.
ICCAD
Marvin Damschen, Lars Bauer, Jörg Henkel
2018 J jnl
Distributed Trade-Based Edge Device Management in Multi-Gateway IoT.
ACM Trans. Cyber Phys. Syst.
Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel
2018 A conf
Highly efficient and accurate seizure prediction on constrained IoT devices.
DATE
Farzad Samie, Sebastian Paul, Lars Bauer, Jörg Henkel
2018 J jnl
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio C. Buttazzo, Jörg Henkel
2017 J jnl
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures.
IEEE Trans. Computers
Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jörg Henkel
2017 — conf
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
SoCC
Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker
2017 J jnl
CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems.
IEEE Embed. Syst. Lett.
Marvin Damschen, Lars Bauer, Jörg Henkel
2017 J jnl
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2017 — conf
Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing.
Euro-Par Workshops
Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat, Michael Bader
2017 J jnl
Timing Analysis of Tasks on Runtime Reconfigurable Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Marvin Damschen, Lars Bauer, Jörg Henkel
2017 A conf
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies).
DATE
Jörg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie
2016 J jnl
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fazal Hameed, Lars Bauer, Jörg Henkel
2016 — conf
Computation offloading and resource allocation for low-power IoT edge devices.
WF-IoT
Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel
2016 J jnl
Dark silicon management: an integrated and coordinated cross-layer approach.
it Inf. Technol.
Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
2016 Misc conf
Distributed QoS management for internet of things under resource constraints.
CODES+ISSS
Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris, Jörg Henkel
2016 J jnl
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors.
ACM Trans. Archit. Code Optim.
Marvin Damschen, Lars Bauer, Jörg Henkel
2016 J jnl
Invasive computing for timing-predictable stream processing on MPSoCs.
it Inf. Technol.
Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
2016 Misc conf
IoT technologies for embedded computing: a survey.
CODES+ISSS
Farzad Samie, Lars Bauer, Jörg Henkel
2016 A* conf
Resource budgeting for reliability in reconfigurable architectures.
DAC
Hongyan Zhang, Lars Bauer, Jörg Henkel
2015 J jnl
Adaptive multi-layer techniques for increased system dependability.
it Inf. Technol.
Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang
2015 A conf
Adaptive on-the-fly application performance modeling for many cores.
DATE
Sebastian Kobbe, Lars Bauer, Jörg Henkel
2015 Misc conf
An approximate compressor for wearable biomedical healthcare monitoring systems.
CODES+ISSS
Farzad Samie, Lars Bauer, Jörg Henkel
2015 — conf
Floating point acceleration for stream processing applications in dynamically reconfigurable processors.
ESTIMedia
Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare, Jörg Henkel
2015 J jnl
Multicast FullHD H.264 Intra Video Encoder Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel
2015 A conf
Online binding of applications to multiple clock domains in shared FPGA-based systems.
DATE
Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel
2015 J jnl
Resource-awareness on heterogeneous MPSoCs for image processing.
J. Syst. Archit.
Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2015 A conf
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.
ICCAD
Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel
2014 J jnl
Adaptive Energy Management for Dynamically Reconfigurable Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammad Shafique, Lars Bauer, Jörg Henkel
2014 J jnl
Adaptive embedded computing with
SIGBED Rev.
Jörg Henkel, Lars Bauer, Artjom Grudnitsky, Hongyan Zhang
2014 Misc conf
Automatic custom instruction identification in memory streaming algorithms.
CASES
Martin Haaß, Lars Bauer, Jörg Henkel
2014 Misc conf
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems.
CASES
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2014 A* conf
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.
DAC
Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel
2014 A conf
MORP: makespan optimization for processors with an embedded reconfigurable fabric.
FPGA
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2014 A* conf
Multi-Layer Dependability: From Microarchitecture to Application Level.
DAC
Jörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique
2014 A* conf
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
DAC
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 A conf
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.
DATE
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 A conf
An H.264 Quad-FullHD low-latency intra video encoder.
DATE
Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel
2013 Misc conf
Hardware acceleration for programs in SSA form.
CASES
Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel
2013 A conf
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
ITC
Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel
2013 Misc conf
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.
CODES+ISSS
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 A* conf
Reliable on-chip systems in the nano-era: lessons learnt and future trends.
DAC
Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
2013 Misc conf
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.
CASES
Fazal Hameed, Lars Bauer, Jörg Henkel
2013 J jnl
Test Strategies for Reliable Runtime Reconfigurable Architectures.
IEEE Trans. Computers
Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich
2012 A conf
Dynamic cache management in multi-core architectures through run-time adaptation.
DATE
Fazal Hameed, Lars Bauer, Jörg Henkel
2012 — conf
Invasive manycore architectures.
ASP-DAC
Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
2012 — conf
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
AHS
Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel
2012 Misc conf
PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors.
FCCM
Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel
2012 A conf
Partial online-synthesis for mixed-grained reconfigurable architectures.
DATE
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2012 C conf
Transparent structural online test for reconfigurable systems.
IOLTS
Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich
2011 Misc conf
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors.
CODES+ISSS
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel
2011 — conf
Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors.
AHS
Lars Bauer, Muhammad Shafique, Jörg Henkel
2011 Misc conf
Design and architectures for dependable embedded systems.
CODES+ISSS
Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
2011 Misc conf
DistRM: distributed resource management for on-chip many-core systems.
CODES+ISSS
Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfgang Schröder-Preikschat, Jörg Henkel
2011 A conf
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors.
DATE
Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jörg Henkel
2011 Misc conf
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.
FCCM
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker
2011 — book
Run-time Adaptation for Reconfigurable Embedded Processors.
Lars Bauer, Jörg Henkel
2011 A conf
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions.
DATE
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel
2010 A conf
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.
DATE
Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel
2010 J jnl
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms.
J. Signal Process. Syst.
Muhammad Shafique, Lars Bauer, Jörg Henkel
2010 A conf
Selective instruction set muting for energy-aware adaptive processors.
ICCAD
Muhammad Shafique, Lars Bauer, Jörg Henkel
2010 A conf
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder.
DATE
Muhammad Shafique, Lars Bauer, Jörg Henkel
2009 A conf
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.
DATE
Muhammad Shafique, Lars Bauer, Jörg Henkel
2009 A conf
Cross-architectural design space exploration tool for reconfigurable processors.
DATE
Lars Bauer, Muhammad Shafique, Jörg Henkel
2009 Misc conf
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.
CODES+ISSS
Lars Bauer, Muhammad Shafique, Jörg Henkel
2009 A conf
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set.
ICCAD
Muhammad Shafique, Lars Bauer, Jörg Henkel
2009 B conf
RISPP: A run-time adaptive reconfigurable embedded processor.
FPL
Lars Bauer, Muhammad Shafique, Jörg Henkel
2009 — —
RISPP: a run-time adaptive reconfigurable embedded processor.
Lars Bauer
2008 A conf
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding.
ISLPED
Muhammad Shafique, Lars Bauer, Jörg Henkel
2008 B conf
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.
FPL
Lars Bauer, Muhammad Shafique, Jörg Henkel
2008 J jnl
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation.
IEEE Trans. Very Large Scale Integr. Syst.
Lars Bauer, Muhammad Shafique, Jörg Henkel
2008 A conf
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set.
DATE
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, Jörg Henkel
2008 A* conf
Run-time instruction set selection in a transmutable embedded processor.
DAC
Lars Bauer, Muhammad Shafique, Jörg Henkel
2007 — conf
A Self-Adaptive Extensible Embedded Processor.
SASO
Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel
2007 — conf
An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms.
ESTIMedia
Muhammad Shafique, Lars Bauer, Jörg Henkel
2007 A* conf
RISPP: Rotating Instruction Set Processing Platform.
DAC
Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel