Larry G. Jones

16 papers A* 5A 1Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
1997 A* conf
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.
DAC
Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernández, Larry G. Jones
1997 — conf
Fast power loss calculation for digital static CMOS circuits.
ED&TC
Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
1996 — conf
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.
ED&TC
Srilata Raman, C. L. Liu, Larry G. Jones
1996 J jnl
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation.
VLSI Design
Srilata Raman, C. L. Liu, Larry G. Jones
1995 — conf
Transistor reordering for low power CMOS gates using an SP-BDD representation.
ISLPD
Alexey Glebov, David T. Blaauw, Larry G. Jones
1994 J jnl
A cache-based method for accelerating switch-level simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Larry G. Jones, David T. Blaauw
1994 — conf
A delay driven FPGA placement algorithm.
EURO-DAC
Srilata Raman, C. L. Liu, Larry G. Jones
1992 J jnl
An incremental zero/integer delay switch-level simulation environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Larry G. Jones
1992 A* conf
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator.
DAC
Larry G. Jones
1991 A* conf
Accelerating Switch-Level Simulation by Function Caching.
DAC
Larry G. Jones
1991 J jnl
Fast batch incremental netlist compilation hierarchical schematics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Larry G. Jones
1991 — conf
Incremental switch-level simulation with zero/integer-delay.
EURO-DAC
Larry G. Jones
1990 J jnl
Efficient Evaluation of Circular Attribute Grammars.
ACM Trans. Program. Lang. Syst.
Larry G. Jones
1989 A* conf
Fast Online/Offline Netlist Compilation of Hierarchical Schematics.
DAC
Larry G. Jones
1989 A conf
Fast incremental netlist compilation of hierarchical schematics.
ICCAD
Larry G. Jones
1986 A* conf
Hierarchical VLSI Design Systems Based on Attribute Grammars.
POPL
Larry G. Jones, Janos Simon