Lana Josipovic

48 papers A* 2A 18B 6Misc 4Journal 7Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS. FPGA Shun Katsumi, Emmet Murphy, Lana Josipovic
2026	—	`conf`	Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. ASPLOS (2) Yann Herklotz, Ayatallah Elakhras, Martina Camaioni, Paolo Ienne, Lana Josipovic, Thomas Bourgeat
2026	A	`conf`	HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs. FPGA Carmine Rizzi, Sebastian Pfeiler, Lana Josipovic
2026	J	`jnl`	Is It a Good Idea to Build an HLS Tool on Top of MLIR? Experience from Building the Dynamatic HLS Compiler. CoRR Jiahui Xu, Emmet Murphy, Lana Josipovic
2025	—	`conf`	CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS. ASPLOS (1) Jiahui Xu, Lana Josipovic
2025	B	`conf`	Compile in Seconds and Run on an FPGA with DynaRapid. FPL Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2025	Misc	`conf`	DRSA: Accelerating Macro Placement on Commercial FPGAs. FCCM Menzo Bouaissi, Paolo Ienne, Lana Josipovic, Andrea Guerrieri
2025	—	`conf`	ElasticMiter: Formally Verified Dataflow Circuit Rewrites. ASPLOS (2) Ayatallah Elakhras, Jiahui Xu, Martin Erhart, Paolo Ienne, Lana Josipovic
2025	A*	`conf`	OptiPIM: Optimizing Processing-in-Memory Acceleration Using Integer Linear Programming. ISCA Jiantao Liu, Minxuan Zhou, Yue Pan, Chien-Yi Yang, Lana Josipovic, Tajana Rosing
2025	A	`conf`	Promise: Property Mining for Sequential Synthesis. ICCAD Jiahui Xu, Jordi Cortadella, Lana Josipovic
2025	—	`conf`	Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis. HEART Mathias Bouilloud, Lana Josipovic, Wayne Luk
2025	A	`conf`	SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. DATE Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic
2024	A	`conf`	Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs. ICCAD Emmet Murphy, Lana Josipovic
2024	B	`conf`	DynaRapid: Fast-Tracking from C to Routed Circuits. FPL Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2024	A	`conf`	DynaRapid: From C to FPGA in a Few Seconds. FPGA Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne
2024	—	`book`	FPGA EDA - Design Principles and Implementation Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipovic, Zhufei Chu
2024	B	`conf`	Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits. FPL Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic
2024	—	`ed.`	Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024, Porto, Portugal, June 19-21, 2024 HEART Lana Josipovic, Peipei Zhou, Shreejith Shanker, João M. P. Cardoso, Jason Anderson, Shibata Yuichiro
2024	A	`conf`	Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. FPGA Jiahui Xu, Lana Josipovic
2024	A	`conf`	Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2023	A*	`conf`	An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. DAC Carmine Rizzi, Andrea Guerrieri, Lana Josipovic
2023	A	`conf`	Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. ICCAD Jiahui Xu, Lana Josipovic
2023	A	`conf`	Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. FPGA Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic
2023	A	`conf`	MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. ICCAD Hanyu Wang, Carmine Rizzi, Lana Josipovic
2023	J	`jnl`	Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides
2023	J	`jnl`	Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2023	A	`conf`	Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2022	—	`conf`	29th Reconfigurable Architectures Workshop (RAW 2022). IPDPS Workshops Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan
2022	B	`conf`	A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic
2022	J	`jnl`	Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
2022	J	`jnl`	DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2022	B	`conf`	Dynamic Inter-Block Scheduling for HLS. FPL Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson
2022	J	`jnl`	From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2022	—	`conf`	Load-Store Queue Sizing for Efficient Dataflow Circuits. FPT Jiantao Liu, Carmine Rizzi, Lana Josipovic
2022	Misc	`conf`	Resource Sharing in Dataflow Circuits. FCCM Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2022	B	`conf`	Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2021	—	`—`	High-Level Synthesis of Dynamically Scheduled Circuits. Lana Josipovic
2021	A	`conf`	Resource Sharing in Dataflow Circuits. FPGA Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2020	A	`conf`	Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
2020	A	`conf`	Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2020	A	`conf`	Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2019	—	`conf`	Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne
2019	A	`conf`	Speculative Dataflow Circuits. FPGA Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2018	A	`conf`	Dynamically Scheduled High-level Synthesis. FPGA Lana Josipovic, Radhika Ghosal, Paolo Ienne
2017	Misc	`conf`	An Out-of-Order Load-Store Queue for Spatial Computing. FCCM Lana Josipovic, Philip Brisk, Paolo Ienne
2017	J	`jnl`	An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. Lana Josipovic, Philip Brisk, Paolo Ienne
2017	Misc	`conf`	From C to elastic circuits. ACSSC Lana Josipovic, Philip Brisk, Paolo Ienne
2016	—	`conf`	Enriching C-based High-Level Synthesis with parallel pattern templates. FPT Lana Josipovic, Nithin George, Paolo Ienne