Lan-Chou Cho

19 papers Journal 9Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage.
IEEE Access
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2024 — conf
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.
AICAS
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2019 J jnl
A 0.85mm
IEEE J. Solid State Circuits
Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2019 — conf
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
ESSCIRC
Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2018 J jnl
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski
2017 J jnl
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits
Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
2016 — conf
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
VLSI Circuits
Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski
2016 J jnl
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits
Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
2014 — conf
28.2 A 0.29mm
ISSCC
YuLi Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai, Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan
2013 — conf
A 0.27mm
ISSCC
Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-Chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski
2011 — conf
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS.
A-SSCC
Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng
2011 J jnl
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC.
IEEE J. Solid State Circuits
Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-Chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien
2011 — conf
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC.
ISSCC
Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-Horng Chen, Lan-Chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien
2009 J jnl
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.
IEEE J. Solid State Circuits
Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu
2008 — conf
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology.
ISSCC
Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
2008 J jnl
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
2007 J jnl
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.
IEEE J. Solid State Circuits
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
2007 — conf
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.
ISSCC
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
2006 — conf
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.
CICC
Chihun Lee, Lan-Chou Cho, Shen-Iuan Liu