Lakshmi N. Reddy

26 papers A* 1A 9C 1Misc 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2022 — conf
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning.
ISPD
Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch
2022 J jnl
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2021 A conf
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.
ICCAD
Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam
2020 — conf
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
ISPD
Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2018 — conf
Interconnect Optimization Considering Multiple Critical Paths.
ISPD
Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam
2018 J jnl
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2016 Misc conf
Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis.
VLSID
Mohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi N. Reddy
2016 — conf
Gate movement for timing improvement on row based Dual-VDD designs.
ISQED
Hua Xiang, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu
2016 A conf
OWARU: free space-aware timing-driven incremental placement.
ICCAD
Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin
2014 J jnl
Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst.
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2013 A conf
Depth controlled symmetric function fanin tree restructure.
ICCAD
Hua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri
2013 A conf
Intuitive ECO synthesis for high performance circuits.
DATE
Haoxing Ren, Ruchir Puri, Lakshmi N. Reddy, Smita Krishnaswamy, Cindy Washburn, Joel Earl, Joachim Keinert
2012 A* conf
GLARE: global and local wiring aware routability evaluation.
DAC
Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2011 J jnl
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev.
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
2010 — conf
Logical and physical restructuring of fan-in trees.
ISPD
Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho
2008 — ch.
Placement-Driven Synthesis Design Closure Tool.
Handbook of Algorithms for Physical Design Automation
Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi N. Reddy, Haoxing Ren, Louise Trevillyan
2004 J jnl
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs.
IEEE Des. Test Comput.
Louise Trevillyan, David S. Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda
2000 A conf
Transformational Placement and Synthesis.
DATE
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
1999 C conf
Performance Driven Optimization of Network Length in Physical Placement.
ICCD
Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy
1996 J jnl
BooleDozer: Logic synthesis for ASICs.
IBM J. Res. Dev.
Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler
1993 J jnl
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1992 A conf
A Small Test Generator for Large Designs.
ITC
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
1992 A conf
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
ICCAD
Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy
1992 — conf
SPADES: a simulator for path delay faults in sequential circuits.
EURO-DAC
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1991 A conf
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
ITC
Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
1991 A conf
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
ICCAD
Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy