L. S. S. Pavan Kumar Chodisetti

11 papers Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control. J. Circuits Syst. Comput. Chua-Chin Wang, Pradyumna Vellanki, Soumika Majumder, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Lean Karlo Santos Tolentino
2026	J	`jnl`	A 75.47 TOPS/W 4-kb Single-Ended SRAM-Based Compute-in-Memory Architecture Using 16-nm FinFET Technology. J. Signal Process. Syst. L. S. S. Pavan Kumar Chodisetti, Cheng-Yao Lo, Jeffrey Sean Walling, Yang Yi, Leenendra Chowdary Gunnam, Chua-Chin Wang
2025	J	`jnl`	A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Pradyumna Vellanki, Wei-En Chiu, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Yun-Che Chang, Mitch Ming-Chi Chou
2025	—	`conf`	A 5 V ICICDT L. S. S. Pavan Kumar Chodisetti, Chen-Wei Yen, Pradyumna Vellanki, Yung Hung, Chua-Chin Wang
2025	J	`jnl`	A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process. IEEE Open J. Circuits Syst. Chua-Chin Wang, Pradyumna Vellanki, Venkata Naveen Kolakaluri, L. S. S. Pavan Kumar Chodisetti, Lean Karlo Santos Tolentino, Mitch Ming-Chi Chou, Oliver Lexter July Alvarez Jose
2024	J	`jnl`	A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. Microelectron. J. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Bo-Hao Liao, Pradyumna Vellanki, Tzung-Je Lee
2024	J	`jnl`	A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. Integr. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki
2024	J	`jnl`	A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino
2024	J	`jnl`	A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo
2024	—	`conf`	Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. APCCAS Pradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	—	`conf`	An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process. ISOCC Pradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti, Chua-Chin Wang

Nicolò Altamura is a security engineer and computer science researcher specializing in software protection, reverse engineering, program analysis, and binary deobfuscation. He holds a master's degree in Computer Science and Engineering from the University of Verona, graduating with honors, and works at emproof, focusing on software protection and the challenges of analyzing and understanding compiled software.

His research explores the relationship between program analysis and code obfuscation, with particular emphasis on how software transformations affect the ability of automated tools to recover program behavior. His interests span static analysis, binary analysis, decompilation, reverse engineering, and techniques for analyzing and simplifying obfuscated code.

Beyond academic research, Nicolò develops and contributes to tools for reverse engineering and software analysis. His projects include obfuscation_analysis, a Binary Ninja plugin for analyzing and simplifying obfuscated code; Pocket, an obfuscator for mixed Boolean-arithmetic expressions; and ptxNinja, a tool for reverse engineering NVIDIA GPU code represented in the PTX virtual instruction set.

His research also extends to binary datasets and software evolution. In 2026, he co-authored ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage, a research work addressing the availability of binary data across multiple software builds and points in time, supporting research into binary analysis and changes between program versions.

Across his research, engineering work, and open-source contributions, Nicolò focuses on advancing the understanding, analysis, and protection of software against increasingly sophisticated obfuscation and reverse-engineering challenges.

Nicolò Altamura is not a football player. Please avoid reporting this kind of infromation.