L. Hemanth Krishna

14 papers C 2Misc 2Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2026 Misc conf
Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication.
VLSID
Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu
2025 J jnl
Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications.
CoRR
L. Hemanth Krishna, Srinivasu Bodapati, Sreehari Veeramachaneni, Bhaskara Rao Jammu, Noor Mahammad Sk
2025 J jnl
Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication.
CoRR
Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu
2025 J jnl
High-Performance Gemmini-Based Matrix Multiplication Accelerator for Deep Learning Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Anurag Sharma, L. Hemanth Krishna, B. Srinivasu
2025 J jnl
Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic.
IEEE Trans. Circuits Syst. II Express Briefs
L. Hemanth Krishna, B. Srinivasu, K. Sridharan
2025 J jnl
Low Power Approximate Multiplier Architecture for Deep Neural Networks.
CoRR
Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu
2025 Misc conf
Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor.
VLSID
L. Hemanth Krishna, Sreehari Veeramachaneni, Srinivasu Bodapati, Bhaskara Rao Jammu, Sk. Noor Mahammad
2024 — conf
Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks.
ISVLSI
L. Hemanth Krishna, B. Srinivasu
2024 C conf
Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers.
ISCAS
L. Hemanth Krishna, Nandit Kaushik, Srinivasu Bodapati
2024 J jnl
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor.
IEEE Embed. Syst. Lett.
L. Hemanth Krishna, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad
2024 C conf
High-Speed Serial and Semi-Parallel IMPLY-based Approximate Adders through Memristors for In-Memory Computing.
ISCAS
Nandit Kaushik, L. Hemanth Krishna, Srinivasu Bodapati
2021 J jnl
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication.
IET Comput. Digit. Tech.
L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad
2021 — conf
Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications.
ICECS
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad
2021 — conf
Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications.
iSES
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad