Kyuseung Han - RankMe

29 papers A 6B 2Journal 12Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. FPL Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee
2025	B	`conf`	NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. FPL Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
2024	J	`jnl`	Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection. J. Syst. Archit. Eunjin Choi, Jina Park, Kyeongwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee
2024	J	`jnl`	Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes. IEEE Trans. Circuits Syst. I Regul. Pap. Jina Park, Kyuseung Han, Eunjin Choi, Jae-Jin Lee, Kyeongwon Lee, Woojoo Lee, Massoud Pedram
2024	—	`conf`	Optimizing Implementation of SNN for Embedded System. ICACT Hyeonguk Jang, Jae-Jin Lee, Kyuseung Han
2024	A	`conf`	STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. ISLPED Kyuseung Han, Hyunseok Kwak, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee
2023	A	`conf`	Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. DATE Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee
2023	A	`conf`	Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. ISLPED Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2022	—	`conf`	Releasing the Memory Bottleneck to Display Video Correctly. ISOCC Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
2021	J	`jnl`	Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes. IEEE Internet Things J. Kyuseung Han, Sukho Lee, Kwang-Il Oh, Younghwan Bae, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2021	J	`jnl`	Developing a Multicore Platform Utilizing Open RISC-V Cores. IEEE Access Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Seung-Yeong Lee, Jae-Hyoung Lee, Woojoo Lee
2021	—	`conf`	K-means Clustering-specific Lightweight RISC-V processor. ISOCC Wooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han
2019	J	`jnl`	A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. IEEE Des. Test Kyuseung Han, Jae-Jin Lee, Woojoo Lee, Jinho Lee
2019	J	`jnl`	MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems. IEEE Access Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee
2019	—	`conf`	Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications. ISOCC Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee
2019	J	`jnl`	TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Woojoo Lee, Taewook Kang, Jae-Jin Lee, Kyuseung Han, Joongheon Kim, Massoud Pedram
2019	A	`conf`	TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. ISLPED Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2018	J	`jnl`	TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyuseung Han, Jae-Jin Lee, Jinho Lee, Woojoo Lee, Massoud Pedram
2017	J	`jnl`	TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management. ACM Trans. Design Autom. Electr. Syst. Woojoo Lee, Kyuseung Han, Yanzhi Wang, Tiansong Cui, Shahin Nazarian, Massoud Pedram
2014	J	`jnl`	Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. Integr. Manhwee Jo, Dongwook Lee, Kyuseung Han, Kiyoung Choi
2014	—	`conf`	Leveraging parallelism in the presence of control flow on CGRAs. ASP-DAC Jihyun Ryoo, Kyuseung Han, Kiyoung Choi
2014	J	`jnl`	Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. IEEE Trans. Dependable Secur. Comput. Kyuseung Han, Ganghee Lee, Kiyoung Choi
2013	A	`conf`	Compiling control-intensive loops for CGRAs with state-based full predication. DATE Kyuseung Han, Kiyoung Choi, Jongeun Lee
2013	—	`conf`	Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. MUE Manhwee Jo, Kyuseung Han, Kiyoung Choi
2013	J	`jnl`	Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. Kyuseung Han, Junwhan Ahn, Kiyoung Choi
2012	A	`conf`	State-based full predication for low power coarse-grained reconfigurable architecture. DATE Kyuseung Han, Seongsik Park, Kiyoung Choi
2011	—	`conf`	A host-accelerator communication architecture design for efficient binary acceleration. ISOCC Yangsu Kim, Kyuseung Han, Kiyoung Choi
2010	—	`conf`	Acceleration of control flow on CGRA using advanced predicated execution. FPT Kyuseung Han, Jong Kyung Paek, Kiyoung Choi
2009	—	`conf`	Coarse-grained reconfigurable architecture for multiple application domains: a case study. ICHIT Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon