Kyung-Sub Son

15 papers C 2Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2020 J jnl
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition.
IEEE Trans. Circuits Syst. II Express Briefs
Kyung-Sub Son, Taek-Joon An, Yong-Hwan Moon, Jin-Ku Kang
2019 J jnl
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Hwan Moon, Jae-Wook Yoo, Young-Soo Ryu, Sang-Ho Kim, Kyung-Sub Son, Jin-Ku Kang
2019 J jnl
Design of a third-order delta-sigma TDC with error-feedback structure.
IEICE Electron. Express
Seong-Mun An, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang
2019 J jnl
Eye-open monitor using two-dimensional counter value profile.
IEICE Electron. Express
Kyung-Sub Son, Yong-Hwan Moon, Sanghun Baek, Namyong Kim, Taek-Joon An, Jin-Ku Kang
2018 — conf
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier.
ISOCC
Min Kim, Kyung-Sub Son, Namhoon Kim, Chang Hang Rho, Jin-Ku Kang
2017 J jnl
A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector.
IEICE Electron. Express
Nguyen Huu Tho, Kyung-Sub Son, Jin-Ku Kang
2016 — conf
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector.
ISOCC
Nguyen Huu Tho, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
2016 J jnl
A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's.
IEICE Electron. Express
Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang
2016 — conf
A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's.
APCCAS
Bum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang
2015 C conf
On-chip jitter tolerance measurement technique for CDR circuits.
ISCAS
Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
2015 J jnl
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR.
IEICE Electron. Express
Kyung-Sub Son, Jin-Ku Kang
2015 J jnl
Precise time-difference repetition for TDC with delay mismatch cancelling scheme.
IEICE Electron. Express
In-Seok Kong, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
2014 J jnl
A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS.
IEICE Electron. Express
Kyongsu Lee, Youngjin Kim, Kyung-Sub Son, Sangmin Lee, Jin-Ku Kang
2014 C conf
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS.
ISCAS
Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang
2014 J jnl
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.
IEICE Electron. Express
Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang