Kyu-Hyoun Kim

22 papers A* 4Journal 9Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads.
ISSCC
Matthew Cohen, Monodeep Kar, Swagath Venkataramani, Viji Srinivasan, Brian Veraa, Matthew M. Ziegler, Nianzheng Cao, Ashish Ranjan, Joel Silberman, Michael Guillorn, Sandra Woodward, JohnDavid Lancaster, Josh Hursey, Kyu-Hyoun Kim, Alberto Mannari, Amrit Nagarajan, Ananda Samajdar, Bahman Hekmatshoartabari, Bob Galbraith, Ching Zhou, David L. Satterfield, Gregory S. Still, Gustavo Tellez, Indira Nair, Indu Masilamanai, Jinwook Jung, Kavi Randhawa, Marcel Schaal, Martin Lutz, Paul Crumley, Philip Jacob, Prasanth Chatarasi, Radhika Jain, Sae Kyu Lee, Sanchari Sen, Sarada Krithivasan, Scot Rider, Shubham Jain, Siyu Koswatta, Thomas Roewer, Tom Gooding, Victor Ferrari, Vidhi Zalani, Zhibin Ren, Kevin Reick, Lisa Maurice, Christopher J. Gonzalez, Chris Catalino, Ryan Nett, Pong-Fei Lu, Robert M. Senger, Leland Chang
2025 J jnl
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits
Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2024 — conf
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
ISSCC
Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2024 — conf
Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning.
ICEIC
Kyu-Hyoun Kim, Mingu Kang
2023 — conf
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
VLSI Technology and Circuits
Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim, Sergey V. Rylov, Jinwook Jung, Seiji Munetoh, Kohji Hosokawa, Xin Zhang, Bahman Hekmatshoartabari, Fabio Carta, Martin Cochet, Robert Casatuta, Mingu Kang, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
2022 J jnl
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits
Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang
2021 — conf
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
ISSCC
Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan
2021 A* conf
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.
ISCA
Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan
2021 — conf
Session 25 Overview: DRAM Memory Subcommittee.
ISSCC
Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim
2020 J jnl
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-Hyoun Kim, Hillery C. Hunter, M. B. Srinivas
2018 A* conf
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
MICRO
Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, Michael B. Healy
2017 A* conf
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
MICRO
Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad
2013 A* conf
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.
ISCA
Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2009 — conf
A 5.4mW 0.0035mm
ISSCC
Kyu-Hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2008 — conf
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator.
ISSCC
Kyu-Hyoun Kim, Paul W. Coteus, Daniel M. Dreps, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
2007 J jnl
A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption.
IEICE Trans. Electron.
Kyu-Hyoun Kim, In-Young Chung
2007 J jnl
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits
Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim
2006 J jnl
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter.
IEEE J. Solid State Circuits
Kyu-Hyoun Kim, Young-Soo Sohn, Chan-Kyoung Kim, Moon-Sook Park, Dong-Jin Lee, Woo-Seop Kim, Changhyun Kim
2006 J jnl
A 512-mb DDR3 SDRAM prototype with C
IEEE J. Solid State Circuits
Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, Jaejun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho
2006 — conf
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
ISSCC
Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim
1999 J jnl
Low-power dynamic termination scheme using NMOS diode clamping.
IEEE J. Solid State Circuits
Dong-Ho Shin, Young-Min Lee, Kyu-Hyoun Kim, Kwyro Lee
1998 J jnl
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS).
IEEE J. Solid State Circuits
Kyu-Hyoun Kim, Kwyro Lee, Tae-Sung Jung, Kang-Deog Suh